Robin Murphy 205577ab6f iommu/io-pgtable-arm: Rationalise MAIR handling ...

Between VMSAv8-64 and the various 32-bit formats, there is either one
64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
As such, keeping two 64-bit values in io_pgtable_cfg has always been
overkill.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>

2019-11-04 19:59:30 +00:00

7.9 KiB

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