Chew, Chiau Ee c50325f7bc spi/pxa2xx: Restore private register bits. ...

The Intel LPSS SPI private register bits have to be restored
when system resume from S3 suspend.

Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

2013-11-28 11:23:37 +00:00

35 KiB

Raw Blame History

View Raw