Mark Brown 37d5993c5c ASoC: Fix WM8996 24.576MHz clock operation ...

Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org

2011-12-11 03:01:09 +08:00

94 KiB

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