Sergei Shtylyov 21ab095cbc clk: renesas: r8a77980: Fix RPC-IF module clock's parent ...

Testing has shown that the RPC-IF module clock's parent is the RPCD2
clock, not the RPC one -- the RPC-IF register reads stall otherwise...

Fixes: 94e3935b57 ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

2019-04-02 10:31:05 +02:00

8.4 KiB

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