Xing Zheng 3e1531dbc3 clk: rockchip: fix the incorrect pclk_edp div width for RK3399 ...

The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

2017-01-18 11:23:36 +01:00

69 KiB

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