Philipp Zabel f7089d923e gpu: ipu-v3: limit pixel clock divider to 8-bits ...

The DI pixel clock divider bit field is only 8 bits wide for the
integer part, so limit the divider to the 1...255 interval before
deciding whether the internal clock can be used and before writing
to the register.

Reported-by: Felix Mellmann <felix.mellmann@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

2015-03-31 12:03:54 +02:00

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