32c4d9e8a4
The msm6242_set()/msm6242_clear() functions are used when writing to Control Register D to set or clear the HOLD bit when reading the current time from the RTC. Doing this with a read-modify-write cycle will potentially clear an interrupt condition which occurs between the read and the write. The datasheet states the following about this: When writing the HOLD or 30 second adjust bits of register D, it is necessary to write the IRQ FLAG bit to a "1". Since the only other bits in the register are the 30 second adjust bit (which is not used) and the BUSY bit (which is read-only), the read-modify-write cycle can be replaced by a simple write with the IRQ FLAG bit set to 1 and the other bits (except HOLD) set to 0. Tested-by: Kars de Jong <jongk@linux-m68k.org> Signed-off-by: Kars de Jong <jongk@linux-m68k.org> Link: https://lore.kernel.org/r/20191116114620.9193-1-jongk@linux-m68k.org Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
6.6 KiB
6.6 KiB