b4b23f08d8
up to 1caeb408f5 ("UPSTREAM: base: soc: Handle custom soc information sysfs entries")
Change-Id: I070748e45a9ffbdd0fdba43fe56b99db90a10b08
Signed-off-by: Matthias Maennich <maennich@google.com>
88 lines
3.5 KiB
Diff
88 lines
3.5 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: David Dai <daidavid1@codeaurora.org>
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Date: Mon, 19 Aug 2019 16:35:44 -0700
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Subject: clk: add pre and post change rate callbacks
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There are scenarios where a rate change could result in a configuration
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change for both the targeted clock and its parent.
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For example, setting the rate for a clock could require both slewing its parent
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PLL as well as adjusting the clock's divider values. Due to the fact that
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rate change propagation always occurs from parent to child, we could exceed
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the allowed operating frequencies for the clock as the parent slews to a higher
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frequency before increasing the downstream divider.
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Add a pre change call back which allows the clock to adjust its divider
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appropriately before any rate change has occurred from its parents to ensure
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that the clock's requirements are always within safe frequencies during parent
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rate changes. The symmetrical post change call back handles the scenario where
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the divider adjusts to a lower value and can only be safely adjusted after the
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parent rate changes.
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Change-Id: I4f8cf9df6fc256d065599de86a34cf99eae4d853
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Signed-off-by: David Dai <daidavid1@codeaurora.org>
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---
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drivers/clk/clk.c | 10 ++++++++++
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include/linux/clk-provider.h | 13 +++++++++++++
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2 files changed, 23 insertions(+)
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diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
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index 1c677d7f7f53..020fdb8105cc 100644
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--- a/drivers/clk/clk.c
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+++ b/drivers/clk/clk.c
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@@ -1980,6 +1980,13 @@ static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
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fail_clk = core;
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}
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+ if (core->ops->pre_rate_change) {
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+ ret = core->ops->pre_rate_change(core->hw, core->rate,
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+ core->new_rate);
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+ if (ret)
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+ fail_clk = core;
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+ }
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+
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hlist_for_each_entry(child, &core->children, child_node) {
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/* Skip children who will be reparented to another clock */
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if (child->new_parent && child->new_parent != core)
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@@ -2082,6 +2089,9 @@ static void clk_change_rate(struct clk_core *core)
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if (core->flags & CLK_RECALC_NEW_RATES)
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(void)clk_calc_new_rates(core, core->new_rate);
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+ if (core->ops->post_rate_change)
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+ core->ops->post_rate_change(core->hw, old_rate, core->rate);
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+
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/*
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* Use safe iteration, as change_rate can actually swap parents
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* for certain clock types.
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diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
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index 2fdfe8061363..73e4369e8408 100644
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--- a/include/linux/clk-provider.h
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+++ b/include/linux/clk-provider.h
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@@ -199,6 +199,13 @@ struct clk_duty {
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* directory is provided as an argument. Called with
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* prepare_lock held. Returns 0 on success, -EERROR otherwise.
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*
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+ * @pre_rate_change: Optional callback for a clock to fulfill its rate
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+ * change requirements before any rate change has occurred in
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+ * its clock tree. Returns 0 on success, -EERROR otherwise.
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+ *
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+ * @post_rate_change: Optional callback for a clock to clean up any
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+ * requirements that were needed while the clock and its tree
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+ * was changing states. Returns 0 on success, -EERROR otherwise.
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*
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* The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
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* implementations to split any work between atomic (enable) and sleepable
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@@ -245,6 +252,12 @@ struct clk_ops {
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struct clk_duty *duty);
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void (*init)(struct clk_hw *hw);
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void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
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+ int (*pre_rate_change)(struct clk_hw *hw,
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+ unsigned long rate,
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+ unsigned long new_rate);
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+ int (*post_rate_change)(struct clk_hw *hw,
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+ unsigned long old_rate,
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+ unsigned long rate);
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};
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/**
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