xiaomi-sm8450/android_kernel_xiaomi_sm8450
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android_kernel_xiaomi_sm8450/drivers/clk/rockchip/clk-rv1108.c
Elaine Zhang 64a1644bc3 clk: rockchip: fix the rv1108 clk_mac sel register description 
The source clock ordering is wrong, as shown in the TRM:
cru_sel24_con[8]
rmii_extclk_sel
clock source select control register
1'b0: from internal PLL
1'b1: from external IO

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-22 02:55:03 +02:00

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