Zhenyu Wang 16a02cf08a agp/intel: fix cache control for sandybridge ...

This is broken from 97ef1bdd0b.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

2010-11-04 09:39:50 +00:00

41 KiB

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