Nicolas Ferre a2a571b74a AT91: pm: make sure that r0 is 0 when dealing with cache operations ...

When using CP15 cache operations (c7), we make sure that Rd (r0)
is actually 0 as ARM 926 TRM is saying.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

2010-10-26 11:32:48 +02:00

7.9 KiB

Raw Blame History

View Raw