Thierry Reding c1d676cec5 clk: tegra: Use the proper parent for plld_dsi ...

The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.

Fixes: b270491eb9 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: Thierry Reding <treding@nvidia.com>

2015-04-10 16:04:22 +02:00

8.4 KiB

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