Andrea Venturi 8f0767611a clk: sunxi: mod1 clock should modify it's parent ...

add CLK_SET_RATE_PARENT to modify the rate on clk upstream

Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

2016-04-22 00:29:21 +02:00

2.0 KiB

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