Russell King aaf4b5d92c ARM: cache-v7: optimise test for Cortex A9 r0pX devices ...

Eliminate one unnecessary instruction from this test by pre-shifting
the Cortex A9 ID - we can shift the actual ID in the teq instruction
thereby losing the pX bit of the ID at no cost.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2015-04-14 22:26:52 +01:00

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