Douglas Leung dc34b05fea MIPS: Fix decoding of c0_config1 for MIPSxx caches with 32 ways per set. ...

This affects certain 4Kc cores.

Signed-off-by: Douglas Leung <douglas@mips.com>
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3855/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2012-07-19 11:23:43 +02:00

38 KiB

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