
Collect cache information from the OF device tree and display it in the cpu hierarchy in sysfs. This is intended to be compatible at the userspace level with x86's implementation[1], hence some of the funny attribute names. The arrangement of cache info is not immediately intuitive, but (again) it's for compatibility's sake. The cache attributes exposed are: type (Data, Instruction, or Unified) level (1, 2, 3...) size coherency_line_size number_of_sets ways_of_associativity All of these can be derived on platforms that follow the OF PowerPC Processor binding. The code "publishes" only those attributes for which it is able to determine values; attributes for values which cannot be determined are not created at all. [1] arch/x86/kernel/cpu/intel_cacheinfo.c BenH: Turned some printk's into pr_debug, added better NULL checking in a couple of places. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
22 KiB
22 KiB