John Crispin c9e854cf94 GPIO: MIPS: lantiq: fix overflow inside stp-xway driver ...

The driver was using a 16 bit field for storing the shadow value of the shift
register cascade. This resulted in only the first 2 shift registeres receiving
the correct data. The third shift register would always receive 0x00.

Fix this by using a 32bit field for the shadow value.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-kernel@vger.kernel.org

2012-09-13 10:31:00 +02:00

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