2a2bf85f05
Pull ARM soc device tree updates from Olof Johansson: "Device tree conversion and enablement branch. Mostly a bunch of new bindings and setup for various platforms, but the Via/Winchip VT8500 platform is also converted over from being 100% legacy to now use device tree for probing. More of that will come for 3.8." Trivial conflicts due to removal of vt8500 files, and one documentation file that was added with slightly different contents both here and in the USb tree. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (212 commits) arm: vt8500: Fixup for missing gpio.h ARM: LPC32xx: LED fix in PHY3250 DTS file ARM: dt: mmp-dma: add binding file arm: vt8500: Update arch-vt8500 to devicetree support. arm: vt8500: gpio: Devicetree support for arch-vt8500 arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices arm: vt8500: clk: Add Common Clock Framework support video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb serial: vt8500: Add devicetree support for vt8500-serial rtc: vt8500: Add devicetree support for vt8500-rtc arm: vt8500: Add device tree files for VIA/Wondermedia SoC's ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support ARM: tegra: Add Avionic Design Medcom-Wide support ARM: tegra: Add Avionic Design Plutux support ARM: tegra: Add Avionic Design Tamonten support ARM: tegra: dts: Add pwm label ARM: ux500: Fix SSP register address format ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT ARM: ux500: Add all encompassing sound node to the HREF Device Tree ...
176 lines
4.4 KiB
C
176 lines
4.4 KiB
C
/*
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* linux/arch/arm/mach-mmp/mmp2.c
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*
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* code name MMP2
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*
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* Copyright (C) 2009 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <asm/hardware/cache-tauros2.h>
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#include <asm/mach/time.h>
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#include <mach/addr-map.h>
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#include <mach/regs-apbc.h>
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#include <mach/cputype.h>
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#include <mach/irqs.h>
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#include <mach/dma.h>
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#include <mach/mfp.h>
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#include <mach/devices.h>
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#include <mach/mmp2.h>
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#include "common.h"
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#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
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static struct mfp_addr_map mmp2_addr_map[] __initdata = {
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MFP_ADDR_X(GPIO0, GPIO58, 0x54),
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MFP_ADDR_X(GPIO59, GPIO73, 0x280),
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MFP_ADDR_X(GPIO74, GPIO101, 0x170),
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MFP_ADDR(GPIO102, 0x0),
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MFP_ADDR(GPIO103, 0x4),
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MFP_ADDR(GPIO104, 0x1fc),
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MFP_ADDR(GPIO105, 0x1f8),
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MFP_ADDR(GPIO106, 0x1f4),
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MFP_ADDR(GPIO107, 0x1f0),
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MFP_ADDR(GPIO108, 0x21c),
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MFP_ADDR(GPIO109, 0x218),
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MFP_ADDR(GPIO110, 0x214),
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MFP_ADDR(GPIO111, 0x200),
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MFP_ADDR(GPIO112, 0x244),
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MFP_ADDR(GPIO113, 0x25c),
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MFP_ADDR(GPIO114, 0x164),
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MFP_ADDR_X(GPIO115, GPIO122, 0x260),
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MFP_ADDR(GPIO123, 0x148),
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MFP_ADDR_X(GPIO124, GPIO141, 0xc),
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MFP_ADDR(GPIO142, 0x8),
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MFP_ADDR_X(GPIO143, GPIO151, 0x220),
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MFP_ADDR_X(GPIO152, GPIO153, 0x248),
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MFP_ADDR_X(GPIO154, GPIO155, 0x254),
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MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
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MFP_ADDR(GPIO160, 0x250),
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MFP_ADDR(GPIO161, 0x210),
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MFP_ADDR(GPIO162, 0x20c),
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MFP_ADDR(GPIO163, 0x208),
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MFP_ADDR(GPIO164, 0x204),
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MFP_ADDR(GPIO165, 0x1ec),
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MFP_ADDR(GPIO166, 0x1e8),
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MFP_ADDR(GPIO167, 0x1e4),
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MFP_ADDR(GPIO168, 0x1e0),
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MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
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MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
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MFP_ADDR(PMIC_INT, 0x2c4),
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MFP_ADDR(CLK_REQ, 0x160),
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MFP_ADDR_END,
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};
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void mmp2_clear_pmic_int(void)
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{
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void __iomem *mfpr_pmic;
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unsigned long data;
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mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
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data = __raw_readl(mfpr_pmic);
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__raw_writel(data | (1 << 6), mfpr_pmic);
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__raw_writel(data, mfpr_pmic);
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}
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void __init mmp2_init_irq(void)
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{
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mmp2_init_icu();
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}
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static int __init mmp2_init(void)
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{
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if (cpu_is_mmp2()) {
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#ifdef CONFIG_CACHE_TAUROS2
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tauros2_init(0);
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#endif
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mfp_init_base(MFPR_VIRT_BASE);
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mfp_init_addr(mmp2_addr_map);
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pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
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mmp2_clk_init();
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}
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return 0;
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}
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postcore_initcall(mmp2_init);
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#define APBC_TIMERS APBC_REG(0x024)
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static void __init mmp2_timer_init(void)
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{
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unsigned long clk_rst;
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__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
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/*
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* enable bus/functional clock, enable 6.5MHz (divider 4),
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* release reset
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*/
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clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
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__raw_writel(clk_rst, APBC_TIMERS);
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timer_init(IRQ_MMP2_TIMER1);
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}
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struct sys_timer mmp2_timer = {
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.init = mmp2_timer_init,
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};
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/* on-chip devices */
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MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
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MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
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MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
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MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
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MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
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MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
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MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
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MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
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MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
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MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
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MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
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MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
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MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
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MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
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MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
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MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
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/* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
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MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
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struct resource mmp2_resource_gpio[] = {
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{
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.start = 0xd4019000,
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.end = 0xd4019fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_MMP2_GPIO,
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.end = IRQ_MMP2_GPIO,
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.name = "gpio_mux",
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mmp2_device_gpio = {
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.name = "pxa-gpio",
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.id = -1,
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.num_resources = ARRAY_SIZE(mmp2_resource_gpio),
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.resource = mmp2_resource_gpio,
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};
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