Jernej Skrabec 55de0f31df clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO ...

CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible
PHY clock parent.

Export it so it can be used later in DT.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

2018-03-02 08:42:30 +01:00

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