Curtis Malainey ba0b3a977e ASoC: rt5677: Set ADC clock to use PLL and enable ASRC ...

Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.

Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>

2019-11-11 13:02:06 +00:00

65 KiB

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