xiaomi-sm8450/android_kernel_xiaomi_sm8450
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android_kernel_xiaomi_sm8450/include/asm-mips/hazards.h
Ralf Baechle a3c4946db4 [MIPS] SB1: Fix interrupt disable hazard. 
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18 16:59:26 +00:00

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