Sohil Mehta f1ac10c24e iommu/vt-d: Add a check for 5-level paging support ...

Add a check to verify IOMMU 5-level paging support. If the CPU supports
supports 5-level paging but the IOMMU does not support it then disable
SVM by not allocating PASID tables.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

2018-01-17 15:02:50 +01:00

17 KiB

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