Sandipan Patra 1d7796bdb6 pwm: tegra: Support dynamic clock frequency configuration ...

Added support for dynamic clock freq configuration in PWM kernel driver.
Earlier the PWM driver used to cache boot time clock rate by PWM clock
parent during probe. Hence dynamically changing PWM frequency was not
possible for all the possible ranges. With this change, dynamic
calculation is enabled and it is able to set the requested period from
sysfs knob provided the value is supported by clock source.

Changes mainly have 2 parts:
  - Tegra186 and later chips [1]
  - Tegra210 and prior chips [2]

For [1] - Changes implemented to set pwm period dynamically and also
          checks added to allow only if requested period(ns) is below or
          equals to higher range.

For [2] - Only checks if the requested period(ns) is below or equals to
          higher range defined by max clock limit. The limitation in
          Tegra210 or prior chips are due to the reason of having only
          one PWM controller supporting multiple channels. But later
          chips have multiple PWM controller instances each having
          single channel support.

Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

2020-06-02 14:25:37 +02:00

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