Shawn Guo 43c9b9e8a4 ARM: imx: set up pllv3 POWER and BYPASS sequentially ...

Currently, POWER and BYPASS bits are set up in a single write to pllv3
register.  This causes problem occasionally from the IPU/HDMI testing.
Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS
sequentially.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

2013-11-11 22:58:45 +08:00

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