The Versatile Express V2P-CA15_A7 (aka TC2) has a CCI-400 which is
needed to get Multi-Cluster Power Management (MCPM) working.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This helps remove asid-to-mm reverse map
While mm->context.id contains the ASID assigned to a process, our ASID
allocator also used asid_mm_map[] reverse map. In a new allocation
cycle (mm->ASID >= @asid_cache), the Round Robin ASID allocator used this
to check if new @asid_cache belonged to some mm2 (from prev cycle).
If so, it could locate that mm using the ASID reverse map, and mark that
mm as unallocated ASID, to force it to refresh at the time of switch_mm()
However, for SMP, the reverse map has to be maintained per CPU, so
becomes 2 dimensional, hence got rid of it.
With reverse map gone, it is NOT possible to reach out to current
assignee. So we track the ASID allocation generation/cycle and
on every switch_mm(), check if the current generation of CPU ASID is
same as mm's ASID; If not it is refreshed.
(Based loosely on arch/sh implementation)
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ASID allocation changes/2
Use the fact that switch_mm() and activate_mm() are exactly same code
now while acknowledging the semantical difference in comment
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ASID allocation changes/1
This patch does 2 things:
(1) get_new_mmu_context() NOW moves mm->ASID to a new value ONLY if it
was from a prev allocation cycle/generation OR if mm had no ASID
allocated (vs. before would unconditionally moving to a new ASID)
Callers desiring unconditional update of ASID, e.g.local_flush_tlb_mm()
(for parent's address space invalidation at fork) need to first force
the parent to an unallocated ASID.
(2) get_new_mmu_context() always sets the MMU PID reg with unchanged/new
ASID value.
The gains are:
- consolidation of all asid alloc logic into get_new_mmu_context()
- avoiding code duplication in switch_mm() for PID reg setting
- Enables future change to fold activate_mm() into switch_mm()
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-Asm code already has values of SW and HW ASID values, so they can be
passed to the printing routine.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This tile-specific API had a minor bug, in that if a super huge (>4GB)
page mapped a particular address range, we wouldn't handle it correctly.
As part of fixing that bug, I also cleaned up some of the pud and pmd
accessors to make them more consistent.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Previously, we used a special-purpose register (SPR_SYSTEM_SAVE_K_0)
to hold the CPU number and the top of the current kernel stack
by using the low bits to hold the CPU number, and using the high
bits to hold the address of the page just above where we'd want
the kernel stack to be. That way we could initialize a new SP
when first entering the kernel by just masking the SPR value and
subtracting a couple of words.
However, it's actually more useful to be able to place an arbitrary
kernel-top value in the SPR. This allows us to create a new stack
context (e.g. for virtualization) with an arbitrary top-of-stack VA.
To make this work, we now store the CPU number in the high bits,
above the highest legal VA bit (42 bits in the current tilegx
microarchitecture). The full 42 bits are thus available to store the
top of stack value. Getting the current cpu (a relatively common
operation) is still fast; it's now a shift rather than a mask.
We make this change only for tilegx, since tilepro has too few SPR
bits to do this, and we don't need this support on tilepro anyway.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
We use the validate_current() API to make sure that "current" seems
plausible before using it. With the new show_regs_print_info()
API, we want to check that current is OK before calling it, since
otherwise we will end up in a recursive panic.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Normally the build doesn't include these warnings, but at one
point I built with -Wsign-compare, and noticed a few things that
are technically bugs. This change fixes those things.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
With this change such sections are grouped with regular text
in the vmlinux image; this change puts them at the front,
which is where the standard Linux includes .text.hot*.
This change should fix a recently-observed bug where a bunch of
symbols were being omitted from the /proc/kallsyms output
because they fell between _etext and _sinittext.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
In strncpy_from_user_asm, when the destination buffer length was the
same as the actual string length, we were returning the size of the
destination buffer. But since it's a NUL terminated string, we should
return the length of the string instead.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Nothing in the codebase was using them, and as written they took
"unsigned long" as the physical address rather than "phys_addr_t",
which is wrong on tilepro anyway. Rather than fixing stale APIs,
just remove them; if there's ever demand for them on this platform,
we can put them back.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
We had been doing an automatic full eviction of the L1 I$
everywhere whenever we did a kernel-space TLB flush. It turns
out this isn't necessary, since all the callers already handle
doing a flush if necessary.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
With this change, tile Linux now supports address-space layout
randomization for shared objects, stack, heap and vdso.
Acked-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Tony Lu <zlu@tilera.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
The r1 value is set based on the r0 value as we return to user space.
So tracing tools won't automatically see the right value. Fix this by
generating the correct r1 value in do_syscall_trace_exit() rather
than trying to tamper with the hot path in syscall return.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
The "available_irqs" value needs to actually reflect the IRQs
available, not just start as an all-ones mask, since we only
have 32 IRQs available even on a 64-bit platform.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This may fix a reported bug where an R_TILEGX_64 in a module was not
pointing to an aligned address.
Reported-by: Simon Marchi <simon.marchi@polymtl.ca>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit adds support for static ftrace, graph function support,
and dynamic tracer support.
Signed-off-by: Tony Lu <zlu@tilera.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Function handles may change while the system was in hibernation
use list pci functions and update the function handles.
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
In rare situations a PCI function can report a busy condition
when we issue the modify pci function command. A temporary busy
condition can exceed 1 second but not 2 seconds. Increase the
time until we report an error to 2 seconds. Also increase the
time we sleep between the retries to reduce the load in this
case.
Suggested-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
List pci functions is used to query and iterate over pci functions.
This function currently has 2 users - initial device discovery and
rescan after a machine check. Instead of having a multipurpose
function pass a callback which gets called for each pci function.
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Some functions that do arch specific resume actions are called
directly from swsusp_asm64.S . Before we add another function call
provide a generic s390_early_resume function which can be used
for this purpose.
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Add an arch specific attribute to recover a pci function from an
error state or config space blockage.
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Use pci_claim_resource to find and request bus ressources in
pcibios_add_device. Also move some (de)initialization stuff to
pcibios_enable_device/pcibios_disable_device.
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This reorganizes the current TLB operations into psuedo-ops to better
pair with MMUv4's native Insert/Delete operations
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
With previous commit freeing up PTE bits, reassign them so as to:
- Match the bit to H/w counterpart where possible
(e.g. MMUv2 GLOBAL/PRESENT, this avoids a shift in create_tlb())
- Avoid holes in _PAGE_xxx definitions
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
From Tony Lindgren:
Omap fixes for the merge window that are not urgent enough
for the -rc series.
* tag 'omap-for-v3.12/fixes-non-critical-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2: use 'int' instead of 'unsigned' for variable 'gpmc_irq_start'
ARM: OMAP2: remove useless variable 'ret'
ARM: OMAP: dma: fix error return code in omap_system_dma_probe()
ARM: OMAP2+: fix wrong address when loading PRM_FRAC_INCREMENTOR_DENUMERATOR_RELOAD
ARM: OMAP2+: am33xx-restart: trigger warm reset on omap2+ boards
ARM: OMAP2: Use a consistent AM33XX SoC option description
ARM: OMAP2+: Remove legacy device creation for McPDM and DMIC
+ Linux 3.11-rc6
This is needed to prevent a build error with a patch queued for fixes
"ARM: OMAP2+: am33xx-restart: trigger warm reset on omap2+ boards".
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
a894fcc2d0 ("ARM: smp_twd: Divorce smp_twd
from local timer API") altered twd_local_timer_common_register() so that it
may make use of late_timer_init.
This is problematic on marzen with Magnus's recent patch "ARM: shmobile:
marzen: Switch to DT_MACHINE_START" which switches marzen around to enable
USE_OF and thus shmobile_timer_init(), which is registered as
late_time_init by shmobile_earlytimer_init() stops being a no-op.
As a work-around I have updated r8a7779_earlytimer_init() so that
shmobile_earlytimer_init() is called after r8a7779_register_twd().
Or in other words, the shmobile_earlytimer_init() setting of
late_time_init overwrites that of twd_local_timer_common_register().
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Magnus Damm <damm@opensource.se>
From Tony Lindgren:
Add basic support for devices on dra7xx by adding the PRCM and hwmod
parts the same way as for other omaps. This is still needed in
addition to device tree support for things like power management.
Via Paul Walmsley <paul@pwsan.com>:
This series adds basic TI DRA7xx PRCM and hwmod support.
Basic test logs are available here:
http://www.pwsan.com/omap/testlogs/dra7xx_prcm_devel_v3.12/20130823050445/
Note that DRA7xx could not be tested locally, since I don't have a board.
* tag 'omap-for-v3.12/dra7xx-prcm' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: DRA7: Enable PM framework initializations
ARM: OMAP: DRA7: hwmod: Create initial DRA7XX SoC data
ARM: OMAP: DRA7: Reuse the omap44xx_restart and fix the device instance
ARM: OMAP: DRA7: powerdomain: Handle missing vc/vp
ARM: OMAP: DRA7: powerdomain: Add DRA7XX data and update header
ARM: OMAP: DRA7: clockdomain: Add DRA7XX data and update header
ARM: OMAP: DRA7: PRCM: Add DRA7XX local MPU PRCM regsiters
ARM: OMAP: DRA7: CM: Add minimal regbit shifts
ARM: OMAP: DRA7: CM: Add DRA7XX register defines
ARM: OMAP: DRA7: PRM: Add DRA7XX register definitions
ARM: DRA7: Add the build support in omap2plus
ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5
ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
ARM: DRA7: board-generic: Add basic DT support
ARM: DRA7: Resue the clocksource, clockevent support
ARM: DRA7: Reuse io tables and add a new .init_early
ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
Signed-off-by: Olof Johansson <olof@lixom.net>
From Tony Lindgren:
OMAP PRCM and hwmod fixes and improvments via Paul Walmsley <paul@pwsan.com>:
Various OMAP PRCM & hwmod fixes and improvements. Notable changes
include:
- a fix for OMAP4 PLL locking to avoid a bootloader dependency that
causes nasty log spew on startup
- AM33xx DEBUGSS support fixes in hwmod data
- OMAP5 mailbox support in hwmod data
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/prcm_a_for_v3.12/20130823125002/
Note that the 3530 failure is due to the mysterious transient serial
issue affecting 3530 for several releases now, which causes a log
parsing failure. PM still seems to work.
* tag 'omap-for-v3.12/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: AM33xx: clock: Add RNG clock data
ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX
ARM: OMAP4: clock: Lock PLLs in the right sequence
ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS
ARM: OMAP2+: Only write the sysconfig on idle when necessary
ARM: OMAP5: hwmod data: Add mailbox data
Signed-off-by: Olof Johansson <olof@lixom.net>
From Rob Herring:
Updates for Highbank for 3.12:
- A couple of fixes to enable LPAE.
- pl08x driver fixes to make it build with ARCH_DMA_ADDR_T_64BIT.
- Avoid L2 related smc calls on Midway.
- Add selecting of necesssary ARM errata.
* tag 'highbank-for-3.12' of git://sources.calxeda.com/kernel/linux:
ARM: highbank: clean-up some unused includes
ARM: highbank: avoid L2 cache smc calls when PL310 is not present
ARM: move outer_cache declaration out of ifdef
ARM: highbank: select ARCH_DMA_ADDR_T_64BIT for LPAE
DMA: fix printk warning in AMBA PL08x DMA driver
DMA: fix AMBA PL08x compilation issue with 64bit DMA address type
ARM: highbank: select required errata work-arounds
ARM: highbank: select ARCH_HAS_HOLES_MEMORYMODEL
ARM: highbank: enable DMA zone for LPAE
ARM: use phys_addr_t for DMA zone sizes
Signed-off-by: Olof Johansson <olof@lixom.net>
From Nicolas Ferre:
AT91 SoC update for 3.12 take 1
- enable kernel uncompress information output for
SoC where it was missing: at91sam9n12 and sama5d3
- addition of at91rm9200 to the generic at91_dt_defconfig
* tag 'at91-soc' of git://github.com/at91linux/linux-at91:
ARM: at91: at91_dt_defconfig: enable rm9200 support
ARM: at91: sam9n12: enable kernel uncompress info output
ARM: at91: sama5: enable kernel uncompress info output
ARM: at91: include sama5d3.h into hardware.h
ARM: at91: sama5d3: add definition for usart base address
From Maxime Ripard:
Allwinner DT changes for 3.12, take 3 and 4
These patches add support for:
- The cubieboard2 board
- The pinctrl driver that got merged for the A20 and A31
- The associated muxing for the A20 and A31 boards already supported
- Enables the gated clocks on the A10s, A20 and A31 DTSI.
* tag 'sunxi-dt-for-3.12-4' of https://github.com/mripard/linux:
ARM: sun7i: Enable the A20 clocks in the DTSI
ARM: sun6i: Enable clock support in the DTSI
ARM: sun5i: dt: Use the A10s gates in the DTSI
ARM: sun7i: Add Cubieboard2 Device Tree
ARM: sun7i: a20-olinuxino: Enable the user LED
ARM: sun7i: a20-olinuxino: Enable UARTs muxing
ARM: sun7i: DT: Add UART muxing options to the DTSI
ARM: sun7i: Add the PIO controller node to the DTSI
ARM: sun6i: colombus: Add uart0 muxing
ARM: sun6i: Add UART0 muxing options
ARM: sunxi: dt: Add PIO controller to A31 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>
For at91 boards, there are different IPs for adc. Different IPs has different
STARTUP & PRESCAL mask in ADC_MR.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Update comment in uaccess.h to reflect the changes for clang support:
gcc only cares about the base register (most architectures don't
encode the size of the operation in the operands like x86 does, and so
it is treated effectively like a register number), whereas clang tries
to enforce the size -- but not for register pairs.
Link: http://lkml.kernel.org/r/1377803585-5913-3-git-send-email-dl9pf@gmx.de
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: Jan-Simon Möller <dl9pf@gmx.de>
From Nicolas Ferre:
AT91 DT changes for 3.12, take 2
- addition of the Nand Flash Controller (NFC) in DT
for sama5d3 SoC. This NFC will enhance the traditional
Nand Flash handling (SMC + PMECC).
* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
ARM: at91/dt: sama5d3xek: reduce the ROM code mapping for pmecc lookup table
ARM: at91/dt: sama5d3xek: Enable NFC support in dts
ARM: at91/dt: sama5d3xek: remove the useless NFC dt parameters
ARM: at91/dt: sam9x5ek: add sound configuration
ARM: at91/dt: sam9x5ek: enable SSC
ARM: at91/dt: sam9x5ek: add WM8731 codec
ARM: at91/dt: sam9x5: add SSC DMA parameters
ARM: at91/dt: add at91rm9200 PQFP package version
ARM: at91: at91rm9200: set default mmc0 pinctrl-names
ARM: at91: at91sam9n12: correct pin number of gpio-key
ARM: at91: at91sam9n12: add qt1070 support
ARM: at91: at91sam9n12: add pinctrl of TWI
ARM: at91: Add PMU support for sama5d3
ARM: at91: at91sam9260: add missing pinctrl-names on mmc
update mach-exynos v2 for v3.12
- enable ARCH_HAS_BANDGAP for exynos SoCs
- always enable PM domains for exynos4x12
- skip C1 cpuidle state for exynos5440
* tag 'samsung-mach-exynos-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12
ARM: EXYNOS: enable ARCH_HAS_BANDGAP
Signed-off-by: Olof Johansson <olof@lixom.net>
From Kukjin Kim:
Update exynos DT:
- fix the RTC DT node name for exynos5250
- update the "status" property of RTC DT node for exynos5250
- add RTC DT node for exynos5420
- add ADC DT node for exynos5420 and exynos5250
Based on previouse exynos DT branch, v3.12-next/dt-exynos
* tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (42 commits)
ARM: dts: add ADC device tree node for exynos5420/5250
ARM: dts: Add RTC DT node to Exynos5420 SoC
ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC
ARM: dts: Fix the RTC DT node name for Exynos5250
ARM: dts: Add USB host node for Exynos4
ARM: dts: add audio clock controller for exynos5420
ARM: dts: Correct the /include entry on exynos5420 dtsi file
ARM: dts: Add MFC node for exynos 5420
ARM: dts: Update 5250 MFC node
ARM: dts: Remove unsused MFC clock from exynos4
ARM: dts: Update clocks entry in MFC binding documentation
ARM: dts: Hook up internal PHY on Arndale
ARM: dts: Enable USB hub on Arndale
ARM: dts: Add secure-firmware boot support for OrigenQaud board
ARM: dts: Add pin state information for DP HPD support to Exynos5420
ARM: dts: Add DP controller DT node to exynos5420 SoC
ARM: dts: Update DP controller DT Node for Exynos5 based SoCs
ARM: dts: Add FIMD DT node to exynos5420 DTS files
ARM: dts: Add basic PM domains for EXYNOS5420
ARM: dts: Update FIMD DT node for Exynos5 SoCs
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Clang does not support the "shortcut" we're taking here for gcc (see below).
The patch uses the macro _ASM_DX to do the job.
From arch/x86/include/asm/uaccess.h:
/*
* Careful: we have to cast the result to the type of the pointer
* for sign reasons.
*
* The use of %edx as the register specifier is a bit of a
* simplification, as gcc only cares about it as the starting point
* and not size: for a 64-bit value it will use %ecx:%edx on 32 bits
* (%ecx being the next register in gcc's x86 register sequence), and
* %rdx on 64 bits.
*/
[ hpa: I consider this a compatibility bug in clang as this reflects a
bit of a misunderstanding about how register strings are used by
gcc, but the workaround is straightforward and there is no
particular reason to not do it. ]
Signed-off-by: Jan-Simon Möller <dl9pf@gmx.de>
Link: http://lkml.kernel.org/r/1377803585-5913-3-git-send-email-dl9pf@gmx.de
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
