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10991 Commits

Author SHA1 Message Date
Kevin Wang
a38470f0f8 drm/amd/powerplay: move power_dpm_force_performance_level to amdgpu_smu file 
because this callback is not asic related function, so move it to top
code level to support more asic (eg: navi10)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Kevin Wang
eefa5e2b30 drm/amd/powerplay: enable uclk dpm default on navi10 
enable uclk (mclk) dpm by default on navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Kenneth Feng
d8ceb192cb drm/amd/powerplay: enable ac/dc feature on navi10 
enable ac/dc feature on navi10. currently we don't have
the case to verify it.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Kenneth Feng
3a3c51dd90 drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10 
on navi10, by default the below four features are enabled.
gfxclk deep sleep: enabled and verified
fw dstate: enabled and then soc ulv is verified
dcefclk deep sleep: enabled and verified. notice that on different boards,
due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk
deep sleep kicking in.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Kevin Wang
c0b9d6d2f1 drm/amd/powerplay: add sclk sysfs interface support for navi10 
miss sclk support in force_clk_levels function

Signed-off-by: Kevin Wang <kevin1.Wang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Tao Zhou
462a70d87e drm/amdgpu: correct reference clock value on navi10 
remove the divisor 4

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Tao Zhou
c877dff7d9 drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure board 
disable DPM UCLK and SOC DS on A0 secure board

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Tao Zhou
fc41915810 drm/amd/powerplay/smu11: add secure board check function (v2) 
To determine whether the board is secure or not.

v2: rebase (Alex)

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Tao Zhou
d7a8efa59b drm/amd/powerplay/smu11: enable ds socclk by default 
Enable soc clk deep sleep.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
d5c316930f drm/amd/powerplay: fix amdgpu_pm_info show gpu load error 
due to the smu dma/RTOS restriction, the interval of catching smu
metric table should be more than 1ms. otherwise it will cause the gpu
activity data corruption.

Signed-off-by:Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
564c4c7f00 drm/amd/powerplay: simplify the interface of get_gpu_power 
this callback function is only call in read_sensor in smu_v11_0.c,
so move this code to {asic}_ppt.c to implement as asic related function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
d573bb214d drm/amd/powerplay: simplify the interface of get_current_activity_percent 
this callback function is only call in read_sensor in smu_v11_0.c,
so move this code to {asic}_ppt.c to implement as asic related function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
e36182490d drm/amd/powerplay: fix dpm freq unit error (10KHz -> Mhz) 
the interface smu_v11_0_get_current_clk_freq should be return 10Khz not
Mhz unit to adapt vega20 and navi10 asic at the same time.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kenneth Feng
162aa5c31a amd/powerplay: update the vcn pg 
update the vcn pg function in navi10.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
9c62f993ee drm/amd/powerplay: add function read_sensor for navi10 
add callback function read_sensor for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
5bbb09943e drm/amd/powerplay: add function set_watermarks_table function for navi10 
add callback function set_watermarks_table for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
4f963b01f6 drm/amd/powerplay: add function notify_smc_display_config_change for navi10 
add callback function notify_smc_display_config_change for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
2d9fb9b066 drm/amd/powerplay: add function get_profiling_clk_mask for navi10 
add callback function get_profiling_clk_mask for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
b45dc20b08 drm/amd/powerplay: add funciton get[set]_power_profile_mode for navi10 (v2) 
add callback function get[set]_power_profile_mode for navi10 asic

v2: fix smu_update_table for rebase (Alex)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
6c6187ece0 drm/amd/powerplay: add function get_workload_type_map for swsmu 
1.add new callback function get_workload_byte for smu
2.remove old workload map function

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
1316b71361 drm/amd/powerplay: remove upload_dpm_level function for vega20 
the function upload_dpm_level is an internal function,
so remove public interface.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
2d589a5bfb drm/amd/powerplay: add function get_fan_speed_percent for navi10 
add callback function get_fan_speed_percent for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
da85f08123 drm/amd/powerplay: add function set_thermal_fan_table for navi10 
add callback function set_thermal_fan_table for navi10 asic

Signed-off-by:Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
4228b6015d drm/amd/powerplay: add function is_dpm_running for navi10 
add callback function is_dpm_running for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
6b1b7b5bf0 drm/amd/powerplay: move read sensor of UVD[VCE]_POWER to amdgpu_smu file 
This part of code is asic unrelated and moves to top code level.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
7447a23b08 drm/amd/powerplay: add function get_current_activity_percent for navi10 
add callback function get_current_activity_percent for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:30 -05:00
Kevin Wang
077ca74e3c drm/amd/powerplay: add function get_gpu_power for navi10 
add callback function get_gpu_power for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
2f72726b2a drm/amd/powerplay: add function unforce_dpm_levels for navi10 
add callback function unforce_dpm_levels for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
50add63bbf drm/amd/powerplay: add funciton force_dpm_limit for navi10 
add callback function force_dpm_limit for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
0a6430da0c drm/amd/powerplay: add function display_configuration_changed for navi10 
1.add callback function to support navi10 asic.
2.Remove unnecessary logical code.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
284305445f drm/amd/powerplay: add function pre_display_config_changed for navi10 
add callback function pre_display_config_changed for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
a43913ea50 drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10 
add callback function get_clock_by_type_with_latency for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
fa51bfc279 drm/amd/powerplay: add function populate_umd_state_clk for navi10 
add callback function populate_umd_state_clk for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
db439ca21b drm/amd/powerplay: add function force_clk_levels for navi10 
add sysfs interface of force_clk_levels sysfs for navi10.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
3366561767 drm/amd/powerplay: add helper function of smu_set_hard_freq_range 
add this function to get dpm clock information.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
0d7cbd2807 drm/amd/powerplay: add helper function of smu_set_soft_freq_range 
add this helper function to get dpm clk information.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
8b3d243e47 drm/amd/powerplay: add helper function of smu_get_dpm_freq_range 
add this helper function to get dpm clk information (min, max);

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
b1e7e22419 drm/amd/powerplay: add function print_clk_levels for navi10 
add sysfs interface of print_clk_levels sysfs for navi10.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
3ac54a5043 drm/amd/powerplay: add helper function to get dpm freq informations 
this function can help driver to get ppclk informations

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
98e1a543c7 drm/amd/powerplay: add function get current clock freq interface for navi10 
add function of get_current_clk_freq_by_table for navi10.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Jack Xiao
bbd7a65350 drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resume 
CSIB BO is required to be pinned down to guarantee
bo is always valid when resume, and to be unpinned it
so that its content can be saved during suspend.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Jack Xiao
2c195b6cac drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactive 
The following KIQ ring test could guarantee the previous unmap
has been done.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Jack Xiao
e17a512a18 drm/amdgpu: RLC must be disabled after SMU when S3 on navi 
SMU requires to interact with RLC when disable all features,
so RLC shouldn't be disabled ahead of SMU.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Jack Xiao
2a8bfa139a drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabled 
MP1 cannot access clock IP during MP1 FW reload, disable PLL
shutdown as a workaround.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
tiancyin
8c3b2d1bc0 drm/amd/powerplay: disable uclk dpm by default 
[why]
The uclk dpm feature is not supported by some certain navi10
board like 18202, while supported by some board like 18201.
It causes modprobe failure on 18202 board.

[how]
Disabled this feature by default, it can be enabled by module parameter
uclk_dpm_support=1.

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Leo Liu
863dd269fa drm/amdgpu/VCN2.0: remove powergating for UVDW tile 
No UVDW tile any more from VCN2.0, so mark out related fields.

It fixes error:
"[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa"

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Kenneth Feng
71322c187c amd/powerplay: enable uclk dpm 
Enable uclk dpm on navi10 as the result of
removing fast switch setting.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Kenneth Feng
687e8ad076 amd/powerplay: fix the issue of uclk dpm 
PPSMC_MSG_SetUclkFastSwitch message can be applied on vega20,
but can't on navi10. This is the prerequisite of uclk dpm on
navi10.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Xiaojie Yuan
c39f3da4e2 drm/amdgpu/gfx10: fix unbalanced MAP/UNMAP_QUEUES when async_gfx_ring is disabled 
gfx_v10_0_kiq_enable_kgq() is called only when async_gfx_ring is
enabled, so should gfx_v10_0_kiq_disable_kgq().

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Xiaojie Yuan
ec171a9302 drm/amdgpu/gfx10: drop redundant se/sh selection 
we already selected se/sh at the beginning of the for loop

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00