Luxul XWR-3150 is a wireless router similar to the XWR-3100 except:
1) It has more RAM
2) Its NAND controller in running in BCH8 mode
3) LAN ports LEDs are hardware controlled
Signed-off-by: Dan Haab <dan.haab@luxul.com>
Acked-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
It is a bit unorthodox to just include a file in the middle of a another
DTS file, it breaks the pattern from other device trees and also makes
it really hard to reference things across the files with phandles.
Restructure the include for the Versatile Express motherboards to happen
at the top of the file, reference the target nodes directly, and indent
the motherboard .dtsi files to reflect their actual depth in the
hierarchy.
This is a purely syntactic change that result in the same DTB files from
the DTS/DTSI files.
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.
This commit adds enable-method properties to all CPU nodes.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.
These registers are used for SMP bringup and CPU hotplugging.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Commit d50f4630c2 ("arm: dts: Remove p1010-flexcan compatible from imx
series dts") removed the fallback compatible "fsl,p1010-flexcan" from
the imx device trees. As the flexcan cores on i.MX25, i.MX35 and i.MX53
are identical, introduce the first as fallback for the two latter ones.
Fixes: d50f4630c2 ("arm: dts: Remove p1010-flexcan compatible from imx series dts")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: linux-stable <stable@vger.kernel.org> # >= v4.16
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Remove the usage of skeleton.dtsi to fix the DTC warnings:
arch/arm/boot/dts/s3c6410-mini6410.dtb: Warning (unit_address_vs_reg):
/memory: node has a reg or ranges property, but no unit name
arch/arm/boot/dts/s3c6410-smdk6410.dtb: Warning (unit_address_vs_reg):
/memory: node has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Remove the usage of skeleton.dtsi to fix the DTC warning:
arch/arm/boot/dts/s3c2416-smdk2416.dtb: Warning (unit_address_vs_reg):
/memory: node has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
As per ARM documentation
PPI(0) ID27 - global timer interrupt is rising-edge sensitive.
set IRQ triggering type to IRQ_TYPE_EDGE_RISING for ARM Global timers.
Fixes: c9ad7bc5fe ("ARM: dts: Enable Broadcom Cygnus SoC")
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This matches licensing used by other BCM5301X files and is preferred as:
1) GPL 2.0+ makes is clearly compatible with Linux kernel
2) MIT is also permissive but preferred over ISC
These files were created and ever touched by a group of four people
only: Felix, INAGAKI, Hauke and me.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Felix Fietkau <nbd@nbd.name>
Acked-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Currently the following error is seen from the CAAM driver:
caam 30900000.caam: device ID = 0x0a16030000000000 (Era -524)
Pass the 'fsl,sec-era' property to properly describe the
era information.
This error happens because the 'fsl,sec-era' is not passed via
device tree.
The era information is used in various places inside drivers/crypto/caam,
so pass the correct version via device tree.
Fixes: 0eeabcad7d ("ARM: dts: imx7s: add CAAM device node")
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The 66AK2G evm has support for dcan.
Add nodes and pinmuxes for dcan0 and dcan1.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Commit 4c9a27a6c6 ("ARM: tegra: Fix ULPI regression on Tegra20") changed
"ulpi-link" clock from CDEV2 to PLL_P_OUT4. Turned out that PLL_P_OUT4 is
the parent of CDEV2 clock and original clock setup of "ulpi-link" was
correct. The reverted patch was fixing USB for one board and broke the
other, now Tegra's clk driver correctly sets parent for the CDEV2 clock
and hence patch could be reverted safely, restoring USB for all of the
boards.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The U8540 was an evolved version of the U8500, but it was never
mass produced or put into products, only reference designs exist.
The upstream support was never completed and it is unlikely that
this will happen so drop the support for now to simplify
maintenance of the U8500.
Cc: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
LPTimer pwm cells should be updated to 3, to allow initialization of
channel, period and polarity.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
In the stm32f4 family, mipi dsi is only supported on stm32f469.
So add a new stm32f469 dtsi file & add mipi dsi support inside.
Signed-off-by: Philippe Cornu <philippe.cornu@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Since commit 83a86fbb5b ("irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE"), a warning is raised if IRQ_TYPE_NONE is used.
So we use IRQ_TYPE_LEVEL_HIGH for usart nodes instead of IRQ_TYPE_NONE.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Fix DTC warnings for stm32mp157:
Warning (unit_address_vs_reg): /soc/pin-controller: node has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): /soc/pin-controller/uart4@0: node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/pin-controller-z: node has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch adds flash nor on qspi. Each flash is
connected in quad mode and has its own chip select.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch adds qspi support on stm32mp157c,
read in memory mapped, write in indirect mode.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add support for USBH (USB Host) to STM32MP157C SoC.
USBH is a USB Host controller supporting the standard registers used for
full- and low-speed (OHCI controller) and high-speed (EHCI controller).
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
This patch enables USBPHYC (USB PHY Controller) on stm32mp157c-ev1.
This enables the two usbphyc usb2 ports.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add support for USBPHYC (USB PHY Controller) to STM32MP157C SoC.
It manages two usb2 ports.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
