The Allwinner A83T is an octacore A7 divided in two clusters of 4 A7,
each cluster having its own regulator and clock.
The operating points were found in Allwinner BSP and fex files.
Note that there are a few OPPs that are missing:
1608000000Hz with 920000mV
1800000000Hz with 1000000mV
2016000000Hz with 1080000mV
These OPPs are pretty unstable but it might be due to the SoC quickly
overheating (till the board completely shuts down).
It seems impossible to reach those frequencies with none or passive
cooling, so better leave them out by default.
It's still possible to add those OPPs on a per-board basis though.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
[maxime: Reordered the nodes alphabetically]
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The Allwinner A83T is a SoC with two clusters of 4 A7, each cluster
having its own regulator and clock.
The regulators are board-specific, thus we need labels for cpu0 and
cpu100 so that we can use references to these nodes from the board
header file.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
According to the i.MX 7Solo/Dual Application Processor Reference
Manual the ECSPI1/2/3, UART1/2/3 and SAI1/2/3 peripherals are
connected through the SPBA bus. Other similar SoCs such as i.MX 6UL
add this bus abstraction. This adds the bus also to the i.MX 7
device tree.
The i.MX SDMA driver uses this abstraction to configure watermark
levels slightly differently, so this might change behavior slightly.
There have no issues been observed before or after the patch.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the Keypad Port module. Add it disabled by default since
only some boards use it. Boards which do need to specify
additional properties as documented in the device tree bindings.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX6UL(L) has a WDOG3 located at start address 0x021E0000 in the
AIPS-2 memory region [1].
[1] i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1,
04/2016, Table-2-3 AIPS-2 memory map, p. 166
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable support for ARM Performance Monitoring Units available
on the Cortex-A7 CPU. There is only a single interrupt for the
PMU in both variants of the family, i.MX 7Solo and 7Dual.
Tested with perf on a i.MX 7Dual:
hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Pass the memory unit-adress to fix the following build warnings with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
There are cases where dts passes an empty memory node, which will be filled
by the bootloader. Passing the memory base address still allows the
bootloader to fill the memory size.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-By: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The ARM PMU doesn't have a reg address, so fix the following DTC warning
(requires W=1):
Node /soc/arm-pmu missing or empty reg/ranges property
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch fixes the following DTC warning (requires W=1):
Node /soc/local_intc simple-bus unit address format error, expected "40000000"
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Jon attempted to fix the amount of RAM on the BCM958625HR in commit
c53beb47f6 ("ARM: dts: NSP: Correct RAM amount for BCM958625HR board")
but it seems like we tripped over some poorly documented schematics.
The top-level page of the schematics says the board has 2GB, but when
you end-up scrolling to page 6, you see two chips of 4GBit (512MB) but
what the bootloader really initializes only 512MB, any attempt to use
more than that results in data aborts. Fix this again back to 512MB.
Fixes: c53beb47f6 ("ARM: dts: NSP: Correct RAM amount for BCM958625HR board")
Acked-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We can never idle the l3_main hwmod so mark the omap_l3_noc node
with ti,no-idle.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can never idle the emif hwmod from within the HLOS so mark the emif
node with ti,no-idle.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can never idle the emif hwmod from within the HLOS so mark the emif
node with ti,no-idle.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add soc node for am4372 with pm-sram phandle to both pm-sram-code and
pm-sram-data regions.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a phandle to point to both the pm-sram-code and pm-sram-data nodes
so that the pm code can locate the sram regions needed to copy low level
PM code.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now that we will use ti-emif-sram driver for am4372 PM, update the
emif DT node with the required sram property.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now that we will use ti-emif-sram driver for am335x PM, update the
emif DT node with the required sram property.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a 'pm_sram_code' reserved region to the ocmcram node to be exposed
by the mmio-sram driver as a pool but also mark it protect-exec so that
it can run code copied to it using sram_exec_copy.
Add another 'pm_sram_data' reserved region to the ocmcram node to act as
the data space for any code running from the 'pm_sram_code' region that
is exposed as a regular pool.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a 'pm_sram_code' reserved region to the ocmcram node to be exposed
by the mmio-sram driver as a pool but also mark it protect-exec so that
it can run code copied to it using sram_exec_copy.
Add another 'pm_sram_data' reserved region to the ocmcram node to act as
the data space for any code running from the 'pm_sram_code' region that
is exposed as a regular pool.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling state of
a CPU cooling device is found by referring to the cpufreq table instead.
Remove the unused properties from the CPU nodes.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This patch adds support for RTC on STM32H743 SoC.
It also adds dt-bindings/interrupt-controller/irq.h include and uses it to
configure RTC alarm interrupt.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch enables USB HS on stm32h743i-eval in OTG (DRD) mode.
The USB connector used will determine the role of USB OTG controller.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch adds support for USB OTG HS and FS on STM32H743 SoC:
-USB OTG HS controller is the same than the one used on STM32F7 SoCs.
-USB OTG FS controller is the same than the one used on STM32F4 SoCs.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch enables USB HS on stm32f749-disco in OTG (DRD) mode.
The USB connector used will determine the role of USB OTG controller.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Configure USB OTG HS in OTG (DRD) mode on STM32746G_eval.
The USB connector used will determine the role of USB OTG controller.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
USB OTG HS on STM32F746 can also be used as Peripheral (gadget), so
this patch adds DWC2 gadget mode fifo sizes bindings.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
The HSE oscillator frequency was wrongly set to 125MHz instead of 25MHz.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch adds SDIO-related DT nodes required by stm32f469 board
There is a hardware issue on these boards, it misses a pullup on
the GPIO line used as card detect to allow correct SD card
detection. To allow correct card detection "broken-cd" property
is used.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Since commit 9273083a15 ("usb: dwc2: Fix TxFIFOn sizes and total TxFIFO
size issues") we could use the OTG mode again.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Add BCM43438 (bluetooth) as a serdev slave device of uart0 (pl011/ttyAMA0).
This allows to automatically insert the bcm43438 to the bluetooth
subsystem instead of relying on patched userspace helpers (hciattach).
In order to keep a debug UART we need to switch to uart1.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Instead of keeping the firmware's pull settings, we better apply
them via the devicetree pin control. Start with the RPi Zero W relevant
first to keep the effort low.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
This stops the driver from trying to probe the ATA slave
interface. The vendor code enables the slave interface
but the driver in the vendor tree does not make use of
it.
Setting it to muxmode 0 disables the slave interface:
the hardware only has the master interface connected
to the one harddrive slot anyways.
Without this change booting takes excessive time, so it
is very annoying to end users.
Fixes: dd5c0561db ("ARM: dts: Add basic devicetree for D-Link DNS-313")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
PMIC node requires external interrupts for proper operation, but property
defining them was missing. This was probably caused by a limited support
for interrupts from more than one parent, which was not possible to define
when support for this board was added. Fix this by adding
'interrupt-extended' property and properly define interrupt lines for PMIC
node.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Fix the unit addresses of PDMA nodes in Exynos5410 (the reg property is
correct) to get rid of DTC warnings like:
arch/arm/boot/dts/exynos5410-odroidxu.dtb: Warning (simple_bus_reg):
Node /soc/amba/pdma@12680000 simple-bus unit address format error, expected "121a0000"
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Typo in unit address of PPMU ACP caused DTC warnings:
arch/arm/boot/dts/exynos4412-odroidu3.dtb:
Warning (simple_bus_reg): Node /soc/ppmu_acp@10ae0000 simple-bus unit address format error, expected "106e0000"
PPMU ACP (under 0x10ae0000 address) is present only in Exynos4210 so
move this node to exynos4210.dtsi with fixing the reg address to proper
one.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
The Ethernet switch has an embedded interrupt controller. Interrupts
from the embedded PHYs are part of this interrupt controller.
Explicitly list the MDIO bus the embedded PHYs are on, and wire up the
interrupts.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
