There is an external resistor divider on PB16, acting like a pull-down,
the pull-up increase power consumption and prevent the vbus detect pin
to reach Vss voltage, ~1.5V mesured on my board, it might not even work
if the pull-up is stronger than usual.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or
USB3 devices. The two first ports can be use for either; both SATA, both
PCIe or one of each in any configuration.
The Third port is only for USB3.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
B2199 HDK is the reference board for STiH418 SoC.
It has the following characteristics:
- 3GB DDR3
- 8GB eMMC / SD-Card slot
- 32MB NOR Flash
- 1 x Gbit Ethernet
- 1 x USB3.0 port
- 2 x USB2.0 ports
- 1 x Sata or Mini-PCIe port
- 1 x WiFi 802.11ac (Quantenna)
- 1 x HDMI out
- 1 x HDMI in
- 1 x SPDIF
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
The STiH418 is advanced UHD 60fps AVC processor with 3D graphic acceleration and
quad-core ARM Cortex A9 CPU.
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This patch adds the DRM/KMS dt nodes.
This node can't be in stih407-family.dtsi file because in the future we
will integrate a new stih418-b2199 board. It's a stih407 family board
with different drm/kms dt nodes.
That is why i created the stih407.dtsi file.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Whenever Suspend PHY bit is set on DRA7x devices,
USB will not work due to Set EP Configuration command
always failing.
This was only found after a recent commit 2164a47 (usb:
dwc3: set SUSPHY bit for all cores, which will be merged
for v3.19) added a missing *required* step to dwc3
initialization. Synopsys Databook requires that we enable
Suspend PHY bit after initialization but that, unfortunately,
breaks DRA7x.
Note that the same regression was already patched for AM437x.
Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
According to v4l2 dt document, we add:
a camera host: ISI port.
a i2c camera sensor: ov2640 port.
to sama5d3xmb.dtsi.
The ov2640 node defines the pinctrls, clocks and refer to isi port.
The ISI node also has a reference to the ov2640 port.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
For sama5d3xmb board, the pins: pinctrl_isi_pck_as_mck is pck1, and
used to provide MCK for camera sensor.
We change its name to: pinctrl_pck1_as_isi_mck.
As we want camera sensor instead of ISI to configure the pck1 (ISI_MCK) pin.
So we remove this pinctrl from ISI DT node. It will be added in sensor's
DT node.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
For sama5d3xmb board, the pins: pinctrl_isi_{power,reset} is used to
power-down or reset camera sensor.
So we should let camera sensor instead of ISI to configure the pins.
This patch will change pinctrl name from pinctrl_isi_{power,reset} to
pinctrl_sensor_{power,reset}. And remove these two pinctrl from ISI's
DT node. We will add these two pinctrl to sensor's DT node.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
As the ISI has 12 data lines, however we only use 8 data lines with
sensor module. So, split the data line into two groups which make
it can be choosed depends on the hardware design.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add nodes for the SRAM available on atmel SoCs
For the at91sam9260 and the at91sam9g20, address mirroring is used to create a
single contiguous SRAM range instead of declaring two separate banks.
Also remove leftover TODOs in the sam9g45 file
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: correct at91sam9rl sram size => 0x10000]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The sama4d4 has Special Function Registers that allow to manage DDR, OHCI, EBI
and AIC interrupt redirection.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: reg size: 0x60]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The sama5d3 has Special Function Registers that allow to manage OHCI, EBI and
the UTMI clock.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: reg size: 0x60]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This D2 led is available for all sama5d3x-ek board. So make it a
heartbeat LED.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Conflicts:
drivers/net/xen-netfront.c
Minor overlapping changes in xen-netfront.c, mostly to do
with some buffer management changes alongside the split
of stats into TX and RX.
Signed-off-by: David S. Miller <davem@davemloft.net>
Merge "mvebu: dt for v3.20" from Andrew Lunn:
mvebu dt changes for v3.20 (part #1)
- Add Armada 388 General Purpose Development Board support
- Add Device Tree description of the Armada 388 SoC
- Document the Device Tree binding for the Armada 388 SoC
- a38x: Add missing labels
- a38x: Add more pinctrl functions
- Add Armada 385 Access Point Development Board support
- Add a number of pinctrl functions
- A38x: Remove redundant pinctrl informations
- a38x: Fix node names
- Add support for Seagate BlackArmor NAS220
- kirkwood: enable phy driver for SATA controller on 88f6192
- gpio_poweroff support for Iomega ix2-200
- Use all remaining MTD space foor rootfs of Iomega ix2-200
* tag 'mvebu-dt-3.20' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Add Armada 388 General Purpose Development Board support
ARM: mvebu: Add Device Tree description of the Armada 388 SoC
ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC
ARM: mvebu: a38x: Add missing labels
ARM: mvebu: a38x: Add more pinctrl functions
ARM: mvebu: Add Armada 385 Access Point Development Board support
ARM: mvebu: Add a number of pinctrl functions
ARM: mvebu: A38x: Remove redundant pinctrl informations
ARM: mvebu: a38x: Fix node names
Kirkwood: add support for Seagate BlackArmor NAS220
ARM: dts: kirkwood: enable phy driver for SATA controller on 88f6192
ARM: dts: add gpio_poweroff support for Iomega ix2-200
ARM: dts: use all remaining MTD space foor rootfs of Iomega ix2-200
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add device nodes for the two SDRAM Bus State Controllers.
The SBSCs are located in the A4BC0 resp. A4BC1 PM domains, which must
not be powered down, else the system will crash.
References to the A4BC0 and A4BC1 PM domains will be added later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the DDR3 Bus State Controller (DBSC3).
The DBSC3 is located in the A4S PM domain, which must not be powered
down, else the system will crash.
This has no visible effect for now, as A4S was never turned off anyway
because its child PM domain A3SM contains the CPU core.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device nodes for the two DDR Bus State Controllers (DBSC).
The DBSCs are located in the A3BC PM domain, which must not be powered
down, else the system will crash.
A reference to the A3BC PM domain will be added later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The regulator core now has support to choose if a regulator
has to be enabled or disabled during system suspend and also
supports changing the regulator operating mode during runtime
and when the system enters into sleep mode.
To lower power during suspend, configure the regulators state
using the same configuration found in the ChromeOS 3.8 kernel
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The Exynos5420 Peach Pit and Exynos5800 Peach Pi boards have a built-in
Silicon Motion USB UVC WebCam whose power supply is the tps65090 fet5
regulator. Since the camera uses the generic USB Video Class driver and
this does not grab a regulator, mark the regulator as always on so the
USB device is enumerated and usable.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The Exynos5420 Peach Pit and Exynos5800 Peach Pi boards have both
a power and lid GPIO keys but only the former was defined in the
DTS. Add DTS snippets for the lid GPIO key too. These were taken
from the downstream ChromeOS 3.8 kernel tree.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The Exynos5250 Snow Chromebook has GPIO keys for power and lid
so the SoC I/O pins have to be configured in external interrupt
mode. Currently, this is working without setting the pinctrl
lines but is better to set it explicitly instead of relying on
the previous state of the I/O pins.
The DTS snippets were taken from the downstream ChromeOS tree.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
On i.MX28, the MDIO bus is shared between the two FEC instances.
The driver makes sure that the second FEC uses the MDIO bus of the
first FEC. This is done conditionally if FEC_QUIRK_ENET_MAC is set.
However, in newer designs, such as Vybrid or i.MX6SX, each FEC MAC
has its own MDIO bus. Simply removing the quirk FEC_QUIRK_ENET_MAC
is not an option since other logic, triggered by this quirk, is
still needed.
Furthermore, there are board designs which use the same MDIO bus
for both PHY's even though the second bus would be available on the
SoC side. Such layout are popular since it saves pins on SoC side.
Due to the above quirk, those boards currently do work fine. The
boards in the mainline tree with such a layout are:
- Freescale Vybrid Tower with TWR-SER2 (vf610-twr.dts)
- Freescale i.MX6 SoloX SDB Board (imx6sx-sdb.dts)
This patch adds a new quirk FEC_QUIRK_SINGLE_MDIO for i.MX28, which
makes sure that the MDIO bus of the first FEC is used in any case.
However, the boards above do have a SoC with a MDIO bus for each FEC
instance. But the PHY's are not connected in a 1:1 configuration. A
proper device tree description is needed to allow the driver to
figure out where to find its PHY. This patch fixes that shortcoming
by adding a MDIO bus child node to the first FEC instance, along
with the two PHY's on that bus, and making use of the phy-handle
property to add a reference to the PHY's.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Merge "ARM: mediatek: DT changes for v3.20 (round 1)" from Matthias Brugger:
This adds support for the mediatek sysirq and the uarts for the following SoCs:
- mt8135
- mt8127
- mt6598
For mt6592 only the sysirq support was added.
* tag 'v3.20-next-dts' of https://github.com/mbgg/linux-mediatek:
ARM: mediatek: dts: Add uart to Aquaris5
ARM: mediatek: dts: Add uart to mt6589
dt-bindings: add mt6592 compatible string for mediatek sysirq
ARM: mediatek: Add sysirq device node to mt6592 dtsi
ARM: mediatek: dts: Add UART dts for MT8127 and MT8135 boards
DTS: serial: Add bindings document for the Mediatek UARTs
ARM: mediatek: add UART dts for mt8127 and mt8135
ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
Current vendor-prefixes.txt already has "ak" prefix for Asahi Kasei Corp
by ae8c4209af2c(of: Add vendor prefix for Asahi Kasei Corp.)
It went through the appropriate review process. But, almost all
Asahi Kasei chip drivers are using "asahi-kasei" prefix today.
(arch/arm/boot/dts/tegra20-seaboard.dts only is using "ak,ak8975",
but there are instances of "asahi-kasei,ak8975" in other dts files.
And drivers/iio/magnetometer/ak8975.c doesn't support "ak,ak8975" prefix)
So, we made a mistake there.
In addition, checkpatch.pl reports WARNING if it is using "asahi-kasei"
prerfix in DT file.
(DT compatible string vendor "asahi-kasei" appears un-documented)
Marking it deprecated and warning with checkpatch is certainly
preferable. So, this patch replace "ak" to "asahi-kasei" in
vendor-prefixes.txt. (and fixup tegra20-seaboard)
OTOH, Asahi Kasei is usually referred to as "AKM", but this patch
doesn't care about it. Because no DT is using that today.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Add handling for gta04 tv out chain:
venc -> opa362 -> svideo
Use invert-polarity in venc node because opa362
is doing polarity inversion also.
Signed-off-by: Marek Belisko <marek@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
CM-T3517, CM-T3530 and CM-T3730 features NAND storage chip connected to
GPMC bus.
Add GPMC DT entry into the root DT file omap3-cm-t3x.dtsi, common for
all three modules.
NAND timings are calculated to be safe for CM-T3x devices as it works
now in non DT boot (in this case the timings are updated by U-Boot).
Update GPMC ranges in boards DT files to include all connected devices.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
CSR atlas7 uses Network on Chip(NoC) bus architecture, there are dozens
of MARCOs, in each MARCO, there are dozens of hardware modules.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Hao Liu <Hao.Liu@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Add device tree node for the Secure Non-Volatile Storage
(SNVS) on the VF610 platform. The SNVS block also has a
Real Time Counter (RTC).
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
I made a mistake when rebasing Andrey Gusakov's patch adding MLB+ clock to the
R8A7791 device tree, inserting <&hp_clk> into the "clocks" property of the
MSTP8 node at a wrong position, so that the input clocks for MLB+ and IPMMU-SGX
got swapped...
Fixes: 7408d3061d ("ARM: shmobile: r8a7791: add MLB+ clock")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up all devices to their respective PM domains.
Add a minimal device node for the Coresight-ETM hardware block, and hook
it up to the D4 PM domain, so the R-Mobile System Controller driver can
keep the domain powered, until the new Coresight code handles runtime
PM.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Renesas sound driver needs #sound-dai-cells settings, but, this usage
is a little bit confusable. It came from ALSA SoC historical reasons.
The sound DAI naming method is different between Single/Multi DAI in
the ALSA framework, and it is used for sound card matching.
And this #sound-dai-cells has relationship to it.
Current SoC dtsi has #sound-dai-cells = <1> as default settings
(= it is assuming that board/platform has multi DAI), and
board/platform side needs to overwrite it if board/platform was single
DAI. This style is more confusable for users.
This patch removes SoC side default settings, and force to set it by
board/platform side.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Renesas sound driver needs #sound-dai-cells settings, but, this usage
is a little bit confusable. It came from ALSA SoC historical reasons.
The sound DAI naming method is different between Single/Multi DAI in
the ALSA framework, and it is used for sound card matching.
And this #sound-dai-cells has relationship to it.
Current SoC dtsi has #sound-dai-cells = <1> as default settings
(= it is assuming that board/platform has multi DAI), and
board/platform side needs to overwrite it if board/platform was single
DAI. This style is more confusable for users.
This patch removes SoC side default settings, and force to set it by
board/platform side.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
