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2668 Commits

Author SHA1 Message Date
Rex Zhu
3411717501 drm/amdgpu: add an implement for check_power_state equal for Si. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:52 -04:00
Rex Zhu
73909a746a drm/amdgpu: add an implement for check_power_state equal for Cz. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:51 -04:00
Rex Zhu
1d516c41d9 drm/amdgpu: add an implement for check_power_state equal for CI 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:50 -04:00
Rex Zhu
fbebf2c6bc drm/amdgpu: add new callback to check power state info 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:50 -04:00
Rex Zhu
db82b67c57 drm/amdgpu: check min clock set by DAL before set ps. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:49 -04:00
Tom St Denis
74f3ce31e9 drm/amd/amdgpu: Put in rest of wave fields 
Add the rest of the basic SQ WAVE fields to
finish off the implementation.  Eventually,
a separate interface will be needed for GPRs.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:49 -04:00
Tom St Denis
472259f026 drm/amd/amdgpu: re-factor debugfs wave reader 
Move IP version specific code into a callback.

Also add support for gfx7 devices.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:48 -04:00
Tom St Denis
394fdde256 drm/amd/amdgpu: Make debugfs write compliment read 
Add PG lock support as well as bank selection to
the MMIO write function.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:47 -04:00
Tom St Denis
32977f93b4 drm/amd/amdgpu: Allow broadcast on debugfs read (v2) 
Allow any of the se/sh/instance fields to be
specified as a broadcast by submitting 0x3FF.

(v2) Fix broadcast range checking

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:47 -04:00
Tom St Denis
5ecfb3b8fc drm/amd/amdgpu: Fix debugfs wave reader 
On non VI/CZ platforms it would not free
the grbm index lock.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:46 -04:00
Tom St Denis
273d7aa13c drm/amd/amdgpu: Add wave reader to debugfs 
Currently supports CZ/VI.  Allows nearly atomic read
of wave data from GPU.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:46 -04:00
Alex Deucher
a125510721 drm/amdgpu: rework IP block registration (v2) 
This makes it easier to replace specific IP blocks on
asics for handling virtual_dce, DAL, etc. and for building
IP lists for hw or tables.  This also stored the status
information in the same structure.

v2: split out spelling fix into a separate patch
    add a function to add IPs to the list

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:45 -04:00
Alex Deucher
cf35c7ca3d drm/amdgpu/powerplay: fix spelling in amdgpu_powerplay.h 
and update a comment as well.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:44 -04:00
Alex Deucher
623fea1868 drm/amdgpu/virtual_dce: move define into source file 
It's not used outside the file.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:44 -04:00
Alex Deucher
2120df475d drm/amdgpu: enable virtual dce on SI 
Add the proper IP module when requested.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:43 -04:00
Alex Deucher
07fecde5d3 drm/amdgpu: fill in vce clock info ioctl query (v2) 
Returns the vce clock table for the user mode driver.
The user mode driver can fill this data into vce clock
data packet for optimal VCE DPM.

v2: update to the new API

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:43 -04:00
Alex Deucher
597be302f1 drm/amdgpu/powerplay: add an implementation for get_vce_clock_state (v3) 
Used by the powerplay dpm code.

v2: update to the new API
v3: drop old include

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:42 -04:00
Alex Deucher
825cc9974d drm/amdgpu/dpm: add an implementation for get_vce_clock_state (v2) 
Used by the non-powerplay dpm code.

v2: update to the new API

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:41 -04:00
Alex Deucher
230cf1ba72 drm/amdgpu/dpm: add new callback to fetch vce clock state (v2) 
Will be used by the new info ioctl query.

v2: fetch a single state per request

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:41 -04:00
Rex Zhu
66ba1afd85 drm/amdgpu: save number of vce states in dpm struct. 
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:40 -04:00
Rex Zhu
0d8de7ca0b drm/amdgpu: use same vce state definition in dpm and powerplay 
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:39 -04:00
Alex Deucher
cf0978819c drm/amdgpu: move dpm related definitions to amdgpu_dpm.h 
No intended functional change.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:38 -04:00
Christian König
7988714237 drm/amdgpu: move align_mask and nop into ring funcs as well (v2) 
They are constant as well.

v2: update uvd and vce phys ring structures as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:38 -04:00
Christian König
21cd942e5c drm/amdgpu: move the ring type into the funcs structure (v2) 
It's constant, so it doesn't make to much sense to keep it
with the variable data.

v2: update vce and uvd phys mode ring structures as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:37 -04:00
Christian König
e12f3d7a23 drm/amdgpu: move IB and frame size directly into the engine description 
I should have suggested that on the initial patchset. This saves us a
few CPU cycles during CS and a bunch of loc.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:36 -04:00
Christian König
7bc6be825a drm/amdgpu: remove explicit NULL init for parse_cs 
sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c

That's just a leftover from radeon.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:36 -04:00
Christian König
e08c90a774 drm/amdgpu: remove 128 NOP hack from vm_flush v2 
With the padding raised to 256 DW that shouldn't be needed any more.

v2: reduce estimation as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:35 -04:00
Christian König
c81b07e6bc drm/amdgpu: remove ring type check for conditional execution 
If a ring doesn't support that it shouldn't implement the function.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:35 -04:00
Christian König
66f3b2d527 drm/amdgpu: pad gfx and compute rings to 256 dw 
The same as on windows to avoid further problems with CE/DE
command submission overlaps.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:34 -04:00
Alex Deucher
a0a71e49f5 drm/amdgpu: clarify why we evict vram twice on suspend 
Update the comment to explain why we do this.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:33 -04:00
Alex Deucher
db9635cc14 drm/amdgpu: used cached gca values for vi_read_register (v2) 
Using the cached values has less latency for bare metal
and SR-IOV, and prevents reading back bogus values if the
engine is powergated.

v2: fix typo in tile idx calculation

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:32 -04:00
Alex Deucher
34817db6c7 drm/amdgpu/gfx8: use cached raster config values in csb setup 
Simplify the code and properly set the csb for harvest values.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:32 -04:00
Alex Deucher
392f0c775c drm/amdgpu/gfx8: cache rb config values 
Needed when for SR-IOV and when PG is enabled.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:31 -04:00
Alex Deucher
e3fa76306f drm/amdgpu: add additional cached gca config variables 
We need to cache some additional values to handle SR-IOV
and PG.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:30 -04:00
Christian König
b88c8796d8 drm/amdgpu: use amdgpu_vm_get_pd_bo in the GEM code 
Instead of messing with the PD directly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:30 -04:00
Christian König
073440d262 drm/amdgpu: move VM defines into amdgpu_vm.h 
Only cleanup, no intended functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:29 -04:00
Christian König
7802301611 drm/amdgpu: move fence and ring defines into amdgpu_ring.h 
Only cleanup, no intended functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:29 -04:00
Christian König
5611350499 drm/amdgpu: move sync handling into a separate header 
Only cleanup, no intended functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:28 -04:00
Christian König
914b4dce4f drm/amdgpu: stop using a bo list entry for the VM PTs 
Saves us a bit of memory.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:28 -04:00
Christian König
f7da30d979 drm/amdgpu: move PT validation back into VM code v2 
Saves a bunch of CPU cycles when swapping things back in and
allows us to split the VM headers into a separate file.

v2: rename parameters

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:27 -04:00
Christian König
a7d64de659 drm/amdgpu: remove adev pointer from struct amdgpu_bo v2 
It's completely pointless to have two pointers to the
device in the same structure.

v2: rename function to amdgpu_ttm_adev, fix typos

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:26 -04:00
Tom St Denis
f3fd451263 drm/amd/amdgpu: Enable UVD PG on Tonga 
Tested by reading tile/clk bits during load/idle.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:26 -04:00
Tom St Denis
97f40ef049 drm/amd/powerplay: Enable UVD powergating for SMU7 
This patch enables detecting VCE/UVD PG features and fixes the
UVD powergate function.

Tested on a Tonga (by reading UVD tile/clk bits during playback/idle).

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:25 -04:00
Christian König
f8991bab1a drm/amdgpu: update the shadow PD together with the real one v2 
Far less CPU cycles needed for this approach.

v2: fix typo

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:25 -04:00
Frank Min
42e8cb5001 drm/amdgpu:wptr poll address of gfx8 is needed 
for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:24 -04:00
Monk Liu
4c2b2453ef drm/amdgpu:properly fix some JumpTable issues 
we found some MEC ucode leads to IB test fail or even
ring test fail if Jump Table of it is not start in
FW bo with page aligned address, fixed by always make
JT address page aligned.

we don't need to patch JT2 for MEC2, because for VI,
MEC2 is a copy of MEC1, thus when converting fw_type
for MEC_JT2 we just return MEC1,hw can use the same
JT for both MEC1 & MEC2.

above two change fixed some ring/ib test failure issue
for some version of MEC ucode.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:23 -04:00
Monk Liu
bed5712e1a drm/amdgpu:add MEC_STORAGE ucode id for sriov 
for sriov, SMC need MEC_STORAGE reserved in fw bo.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Frank Min <frank.min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:23 -04:00
Frank Min
ac00bbf32b drm/amdgpu:add callback in cgs for sriov detect 
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:22 -04:00
Frank Min
f501a7e550 drm/amdgpu:fw bo should be in VRAM for SRIOV 
for GTT memory SMC can only access it within PF space, which is not
used for SRIOV case, thus for SRIOV case, we let SMC use FB space for
ucode bo.

Signed-off-by: Frank Min <frank.min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:22 -04:00
Frank Min
01ab960d49 drm/amdgpu:keep bo pinned in prefered domain 
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-10-25 14:38:21 -04:00