Alex Deucher db9635cc14 drm/amdgpu: used cached gca values for vi_read_register (v2) ...

Using the cached values has less latency for bare metal
and SR-IOV, and prevents reading back bogus values if the
engine is powergated.

v2: fix typo in tile idx calculation

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2016-10-25 14:38:32 -04:00

..

acp

drm/amd: add Kconfig dependency for ACP on DRM_AMDGPU

2016-05-25 09:44:15 -04:00

amdgpu

drm/amdgpu: used cached gca values for vi_read_register (v2)

2016-10-25 14:38:32 -04:00

amdkfd

Merge tag 'v4.8-rc8' into drm-next

2016-09-28 12:08:49 +10:00

include

drm/amdgpu:add MEC_STORAGE ucode id for sriov

2016-10-25 14:38:23 -04:00

powerplay

drm/amd/powerplay: Enable UVD powergating for SMU7

2016-10-25 14:38:25 -04:00

scheduler

drm/amdgpu: fix timeout value check in amd_sched_job_recovery

2016-08-19 12:29:20 -04:00