This patch adds the Hisilicon Fast Ethernet MAC(FEMAC) driver.
The FEMAC supports max speed 100Mbps and has been used in many
Hisilicon SoC.
Signed-off-by: Dongpo Li <lidongpo@hisilicon.com>
Reviewed-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The MDP4/5 DT node now contains a list of ports that describe how it
connects to external encoder interfaces like DSI and HDMI. These follow
the standard of_graph bindings, and allow us to get rid of the 'connectors'
phandle that contained a list of all the external encoders connected to
MDP.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Add a new doc for DT bindings for platforms that contain MDP5 display
controller hardware. The doc describes bindings for the top level
MDSS wrapper hardware and MDP5 itself.
Add an example for the bindings as found in MSM8916.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
MDP4 and MDP5 vary a bit in terms of device hierarchy and the properties
they require. Rename the binding doc to mdp4.txt and remove MDP5 specific
pieces. A separate document will be created for MDP5
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Some cleanups:
- Use simpler names for DT nodes in the example
- Use references instead of dumping Document links everywhere
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel
clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC
uses these as source clocks for some of its RCGs to generate clocks that
finally feed to the DSI host controller.
Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to
the DSI host. Use the DSI PHY provided clocks to set up the parents
of these assigned clocks.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The DSI node now has two ports that describe the connection between the
MDP interface output and the DSI input, and the connection between the DSI
output and the connected panel/bridge. Update the properties and the
example.
Also, use generic PHY bindings instead of the custom one.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The "qcom,data-lane-map" binding mentioned in the document is changed to
the more generic "data-lanes" property specified in:
Documentation/devicetree/bindings/media/video-interfaces.txt
The previous binding expressed physical to logical data lane mappings,
the standard "data-lanes" binding uses logical to physical data lane
mappings. Update the docs to reflect this change. The example had the
property incorrectly named as "lanes", update this too.
The MSM DSI DT bindings aren't used anywhere at the moment, so
it's okay to update this property.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Address some issues wiht clock related bindings. It's okay to change these
since these bindings aren't used in any dtsi files until now.
MDP5:
- Don't ask for source clock
MDP4:
- Give a better name for MDP_TV_CLK
- Remove TV_SRC
- Add MDP_AXI_CLK
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drm/panel: Changes for v4.8-rc1
This set of changes contains a few cleanups for existing panels as well
as improved handling of certain backlights. In addition there's support
for a few new simple panels.
* tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/panel: simple: Add support for Starry KR122EA0SRA panel
dt-bindings: Add Starry KR122EA0SRA panel binding
dt-bindings: Add vendor prefix for Starry
dt-bindings: display: Add Sharp LQ101K1LY04 panel binding
drm/panel: simple: Add support for Sharp LQ101K1LY04
drm/panel: simple: Add support for LG LP079QX1-SP0V panel
dt-bindings: Add support for LG LP079QX1-SP0V panel
drm/panel: simple: Add support for Sharp LQ123P1JX31 panel
dt-bindings: Add Sharp LQ123P1JX31 panel binding
drm/panel: simple: Add support for Samsung LSN122DL01-C01 panel
dt-bindings: Add Samsung LSN122DL01-C01 panel binding
drm/panel: simple: Add support for LG LP097QX1-SPA1 panel
dt-bindings: Add LG LP097QX1-SPA1 panel binding
drm/panel: simple: Update backlight state property
drm/panel: simple: Remove gratuitous blank line
drm/panel: simple: Fix a couple of physical sizes
drm/tegra: Changes for v4.8-rc1
This set of changes contains a bunch of cleanups to the host1x driver as
well as the addition of a pin controller for DPAUX, which is required by
boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C
mode (for HDMI and DDC).
Included is also a bit of rework of the SOR driver in preparation to add
DisplayPort support as well as some refactoring and cleanup.
Finally, all output drivers are converted to runtime PM, which greatly
simplifies the handling of clocks and resets.
* tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits)
drm/tegra: sor: Reject HDMI 2.0 modes
drm/tegra: sor: Prepare for generic PM domain support
drm/tegra: dsi: Prepare for generic PM domain support
drm/tegra: sor: Make XBAR configurable per SoC
drm/tegra: sor: Use sor1_src clock to set parent for HDMI
dt-bindings: display: tegra: Add source clock for SOR
drm/tegra: sor: Implement sor1_brick clock
drm/tegra: sor: Implement runtime PM
drm/tegra: hdmi: Implement runtime PM
drm/tegra: dsi: Implement runtime PM
drm/tegra: dc: Implement runtime PM
drm/tegra: hdmi: Enable audio over HDMI
drm/tegra: sor: Do not support deep color modes
drm/tegra: sor: Extract tegra_sor_mode_set()
drm/tegra: sor: Split out tegra_sor_apply_config()
drm/tegra: sor: Rename tegra_sor_calc_config()
drm/tegra: sor: Factor out tegra_sor_set_parent_clock()
drm/tegra: dpaux: Add pinctrl support
dt-bindings: Add bindings for Tegra DPAUX pinctrl driver
drm/tegra: Prepare DPAUX for supporting generic PM domains
...
This patch rework the output code to add of_graph dt binding support
for panel device and also keeps the backward compatibility
Signed-off-by: Meng Yi <meng.yi@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Pull NAND changes from Boris Brezillon:
"""
This pull request contains only one notable change:
* Addition of the MTK NAND controller driver
And a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* A few fixes/improvements for the xway NAND controller driver
* A few fixes for the sunxi NAND controller driver
* Support for DMA in the sunxi NAND driver
* Support for the sunxi NAND controller IP embedded in A23/A33 SoCs
* Addition for bitflips detection in erased pages to the brcmnand driver
* Support for new brcmnand IPs
* Update of the OMAP-GPMC binding to support DMA channel description
"""
We can't detect the FXEN (fiber mode) bootstrap pin, so configure
it via a boolean device tree property "micrel,fiber-mode".
If it is enabled, auto-negotiation is not supported.
The only available modes are 100base-fx (full duplex and half duplex).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
Addition of device tree support for DA9210.
Two files are modified, the driver source file and the binding document.
Updates for the regulator source file include an .of_match_table entry and
node match checking in the probe() function for a compatible da9210 string.
Minor binding documentation changes have been made to the title and the
example.
Tested-by: Steve Twiss <stwiss.opensource@diasemi.com>
Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The endpoint nodes have a reg property, they also need a unit-address. Add
them in the example.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The trigger doesn't need the reg property. When it is not defined, the node
name doesn't need a unit-address. Remove them from the example.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The samsung,exynos5433-spi has some peculiarities that bring the
need of creating a new compatible in the binding.
One of those is the 3-clocks controller management where the spi
is fed with three clocks: "spi", "busclkN" and "ioclk".
By adding the exynos5433-spi, we deprecate the exynos7 compatible
and discourage its use.
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Merging this in avoids a build error that was missed earlier:
In file included from ../arch/arm/boot/dts/meson8b-mxq.dts:48:0:
../arch/arm/boot/dts/meson8b.dtsi:49:53: fatal error: dt-bindings/reset/amlogic,meson8b-reset.h: No such file or directory
* reset/for-4.8-2:
dt-bindings: reset: Add bindings for the Meson SoC Reset Controller
reset: Add support for the Amlogic Meson SoC Reset Controller
reset: Return -ENOTSUPP when not configured
reset: oxnas: Use devm register API and get rid of platform remove
reset: fix Kconfig menu to include reset drivers in sub-menu
reset: zynq: use devm_reset_controller_register()
reset: socfpga: use devm_reset_controller_register()
reset: sunxi: use devm_reset_controller_register()
reset: pistachio: use devm_reset_controller_register()
reset: ath79: use devm_reset_controller_register()
reset: add devm_reset_controller_register API
This is needed to work around another failure with "make dtbs":
In file included from ../arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts:12:0:
arch/arm64/boot/dts/renesas/r8a7796.dtsi:13:44: fatal error: dt-bindings/power/r8a7796-sysc.h: No such file or directory
* renesas/rcar-sysc:
soc: renesas: rcar-sysc: Add support for R-Car M3-W power areas
soc: renesas: Add r8a7796 SYSC PM Domain Binding Definitions
soc: renesas: rcar-sysc: Document r8a7796 support
This is required to avoid a 'make dtbs' failure:
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:47:56: fatal error: dt-bindings/reset/amlogic,meson-gxbb-reset.h: No such file or directory
The dependency was not handled right earlier, I'm fixing up the branch here
to minimize the bisection problem.
* reset/for-4.8-2:
dt-bindings: reset: Add bindings for the Meson SoC Reset Controller
reset: Add support for the Amlogic Meson SoC Reset Controller
reset: Return -ENOTSUPP when not configured
reset: oxnas: Use devm register API and get rid of platform remove
reset: fix Kconfig menu to include reset drivers in sub-menu
reset: zynq: use devm_reset_controller_register()
reset: socfpga: use devm_reset_controller_register()
reset: sunxi: use devm_reset_controller_register()
reset: pistachio: use devm_reset_controller_register()
reset: ath79: use devm_reset_controller_register()
reset: add devm_reset_controller_register API
The SOR clock can have various sources, with the most commonly used
being the sor_safe, pll_d2_out0, pll_dp and sor_brick clocks. These
are configured using a three level mux, of which the first 2 levels
can be treated as one. The direct parents of the SOR clock are the
sor_safe, sor_brick and sor_src clocks, whereas the pll_d2_out0 and
pll_dp clocks can be selected as parents of the sor_src clock via a
second mux.
Previous generations of Tegra have only supported eDP and LVDS with
the SOR, where LVDS was never used on publicly available hardware.
Clocking for this only ever required the first level mux (to select
between sor_safe and sor_brick).
Tegra210 has a new revision of the SOR that supports HDMI and hence
needs to support the second level mux to allow selecting pll_d2_out0
as the SOR clock's parent. This second mux is knows as sor_src, and
operating system software needs a reference to it in order to select
the proper parent.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Kishon writes:
phy: for 4.8 -rc1
*) Add a new phy_ops for setting the phy mode
*) Add a new phy driver for DA8xx SoC USB PHY
*) Minor fixes and cleanups
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* topic/vsp1: (36 commits)
[media] v4l: vsp1: wpf: Add flipping support
[media] v4l: vsp1: rwpf: Support runtime modification of controls
[media] v4l: vsp1: Simplify alpha propagation
[media] v4l: vsp1: clu: Support runtime modification of controls
[media] v4l: vsp1: lut: Support runtime modification of controls
[media] v4l: vsp1: Support runtime modification of controls
[media] v4l: vsp1: Add Cubic Look Up Table (CLU) support
[media] v4l: vsp1: lut: Expose configuration through a control
[media] v4l: vsp1: lut: Initialize the mutex
[media] v4l: vsp1: dl: Don't free fragments with interrupts disabled
[media] v4l: vsp1: Set entities functions
[media] v4l: vsp1: Don't create LIF entity when the userspace API is enabled
[media] v4l: vsp1: Don't register media device when userspace API is disabled
[media] v4l: vsp1: Base link creation on availability of entities
[media] media: Add video statistics computation functions
[media] media: Add video processing entity functions
[media] v4l: vsp1: sru: Fix intensity control ID
[media] v4l: vsp1: Stop the pipeline upon the first STREAMOFF
[media] v4l: vsp1: Constify operation structures
[media] v4l: vsp1: pipe: Fix typo in comment
...
Provide generic bindings for all Jedec JC-42.4 compatible temperature
sensor chips.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
This commit adds the Device Tree binding documentation for the Marvell
XOR v2 engine, which is found on Marvell Armada 7K/8K ARM64 SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Update the SRAB, core driver and binding document to support the
BCM585xx/586xx/88312 integrated switch (Northstar Plus SoCs family).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Sharp LQ101K1LY04 is a 10" WXGA (1280x800) LVDS panel and is
compatible with the simple-panel binding.
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD
panel connected using eDP interfaces.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has 8 different PWM controllers and each controller has only
one output. Earlier SoC generations have 4 PWM outputs per controller.
Add a device tree compatible string for Tegra186 to be able to
differentiate between the two.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
