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15334 Commits

Author SHA1 Message Date
James Zhu
df3183b37a drm/amdgpu: fix typo for vcn3/jpeg3 idle check 
fix typo for vcn3/jpeg3 idle check

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Likun Gao
86a9eb3f59 drm/amd/powerplay: enable FCLK DS for sienna_cichlid 
Enable the feature of FCLK Deep Sleep for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Likun Gao
d0d7197086 drm/amd/powerplay: enable VR0HOT for sienna_cichlid 
Enable the feature of Voltage Regulator (VR) Hot for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
shaoyunl
adab4dadd9 drm/amdkfd: sienna_cichlid virtual function support 
amdkfd add support for sienna_cichlid virtual function

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Jay Cornwall
3cefc7189c drm/amdkfd: Support debugger in Navi1x trap handler 
- Preserve scalar GPRs ttmp[4:11] and ttmp13
- Add single step exception during context save workaround
- Remove incorrect PC adjustment during context save

Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Jay Cornwall
d0f1a85366 drm/amdkfd: Support newer assemblers in gfx10 trap handler 
The contents of macros are parsed by the assembler before conditions
have been tested. This causes assembly errors when using IP-specific
instructions in the IP-unified trap handler.

Add a preprocessing step to filter IP-specific code.

Also guard a Navi1x-specific instruction (no effect on Sienna_Cichlid).

Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Jay Cornwall
80b6cfedd3 drm/amdkfd: Add Sienna_Cichlid trap handler support 
- Replace SQC stores with TCP stores
- Synchronize with MSG_SAVEWAVE via lgkmcnt
- HW_REG_IB_STS is now read-only

Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Yong Zhao
3a2f0c813b drm/amdkfd: Support Sienna_Cichlid KFD v4 
v4: drop get_tile_config, comment out other callbacks

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Jerry (Fangzhi) Zuo
81d9bfb8c5 drm/amdgpu/dc: Add missing Sienna_Cichlid chip id 
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
689dede0a0 drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid 
Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
1f5d9cad08 drm/amdgpu: fix SDMA hdp flush engine conflict 
Each of HDP flush engine should be used by one ring, correct allocate of
hdp flush engine to SDMA ring.
Correct me value of each SDMA ring, as it was cleared when init microcode.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
98f8ea29ff drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid. 
Enable mmhub clockgating.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
bcc8367f94 drm/amd/amdgpu: add athub ls support 
athub ls is bounded with hdp ls,verified.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
3a32c25a8e drm/amd/amdgpu: add IH cg support 
IH cg verified

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
ca36461f42 drm/amd/amdgpu: add HDP mgcg and ls support 
add HDP mgcg and ls support and verified

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
91c6adf873 drm/amd/amdgpu: fix the HDP LS/DS/SD programming 
confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN
have to be set for SRAM LS/DS/SD

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
850e56ba44 drm/amdgpu: update golden setting for gfx10.3 
Update gfx golden setting for gfx10.3.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Leo Liu
d6b0185b8d drm/amdgpu: set the LMI ctrl and reset earlier 
So the LMI register will be programmed properly

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Leo Liu
07d8e891ff drm/amdgpu: fix the PSP front door loading VCN firmware 
for the second instance with correct index

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Leo Liu
14765e9c22 drm/amdgpu: change the offset for VCN FW cache window 
The signed header is added

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
00194def45 drm/amdgpu: open GFX clock gating for sienna_cichlid 
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
87ba7feafa drm/amdgpu: switch to query reserved fb size from vbios (v3) 
For Sienna_Cichlid, query fw_reserved_fb_size from vbios directly.
For navi1x, fall back to default 64K TMR size.
For pre-navi, no need to reserve tmr region in top LFB.

v2: fix TMR define (Alex)
v3: partially revert size change

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
9a244ebe81 drm/amdgpu: add atomfirmware helper funciton to query reserved fb size 
fw_reserved_size_in_kb is introduced for driver to query
the TMR region reserved by PSP BL in Sienna_Cichlid and onwards

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
718715e6a4 drm/amdgpu: add firmware_info v3_4 structure for Sienna_Cichlid 
firmware_info v3_4 strucure will be used by kernel driver
to query various parameters set by VBIOS for Sienna_Cichlid

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
738c822c7f drm/amdgpu: only send one sdma firmware for sienna_cichlid 
As all four sdma firmware are same, PSP only receive one SDMA fw.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
321b3eeb77 drm/amdgpu: drop gfx_v10_0_tiling_mode_table_init 
tiling mode table is not used anymore for gfx10

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
8b41903a2b drm/amdgpu: support query vram info for sienna_cichlid 
support query vram_module v11 and vram_info v2_5
for sienna_cichlid

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Hawking Zhang
9d3708169f drm/amdgpu: add vram_info v2_5 in atomfirmware header 
vram_info v2_5 was introduced to support sienna_cichlid

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
f95c20464d drm/amdgpu: disable gfxoff for sienna_cichlid 
Temporary disable gfxoff for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
0f7ee05750 drm/amdgpu: add cp firmware backdoor loading triger 
Triger CP ucode addr and data to backdoor load CP firmware.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Hawking Zhang
305401e77b drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3 
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
263acd471f drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid 
Add gc golden setting for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
4d72dd12f0 drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid 
By adding JPEG HW block to Sienna_Cichlid

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b467c4f5b4 drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid 
By setting up the flags to the ASIC

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b52e271e15 drm/amdgpu: add Sienna_Cichlid JPEG PG and CG support 
This is for static powergating and clockgating

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
dfd57dbf44 drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid 
With basic IP block functions and ring functions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b8f10585cb drm/amdgpu: enable VCN3.0 for Sienna_Cichlid 
By adding VCN HW block to Sienna_Cichlid

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
265120abc0 drm/amdgpu: add Sienna_Cichlid VCN to the VCN family 
By adding Sienna_Cichlid VCN firmware

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
e823be13db drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid 
By setting up the flags to the ASIC

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
fedac0155a drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2) 
This is for static powergating and clockgating

v2: fix registers (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
cf14826cdf drm/amdgpu: add VCN3.0 support for Sienna_Cichlid 
With basic IP block functions and ring functions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
25fc05648f drm/amdgpu/mes: correct register offset for sienna_cichlid 
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
83a0c342e0 drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid 
The number of queue per pipe for mec on sienna_cichlid should be 4.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Jack Xiao
a346ef86a9 drm/amdgpu: add mes block to sienna_cichlid 
Add mes block support to sienna_cichlid.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Jack Xiao
9ed60748fb drm/amdgpu/mes10.1: update mes initialization 
Update mes initialization sequence.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
03195e8063 drm/amdgpu: no need to set up GPU scheduler for mes ring 
As mes ring directly submits to hardwared,
it's no need to set up GPU scheduler for mes ring.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
93fd978b2b drm/amdgpu/psp: convert amdgpu mes ucode type 
Convert to psp defined ucode item, so that psp can recognize them.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
aa1faaa1fc drm/amdgpu: upload mes firmware to gpu buffer 
Copy mes firmware to gpu buffer.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
6b8199fc1a drm/amdgpu/mes10.1: copy mes fw info into global fw array 
Copy mes firmware info into into global fw array, preparing
for fw front door loading.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
f85f1864b8 drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support 
Add sienna_cichlid mes firmware support.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00