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3154 Commits

Author SHA1 Message Date
Ken Wang
d4196f011c drm/amdgpu: add vega10 chip name 
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:32 -04:00
Ken Wang
8e3153ba3f drm/amdgpu: add common soc15 headers 
These are used by various IP modules.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:31 -04:00
Alex Deucher
90df1d55a2 drm/amdgpu: add SDMA 4.0 packet header 
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:30 -04:00
Alex Deucher
6a38ce8f19 drm/amdgpu: add gfx9 clearstate header 
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:30 -04:00
Felix Kuehling
4b219123e9 drm/amd: Add MQD structs for GFX V9 
This header defines the gfx v9 MEC structures.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:29 -04:00
Alex Deucher
f6c3947893 drm/amdgpu: add the VCE 4.0 register headers 
These are the Video Compression Engine registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:28 -04:00
Alex Deucher
7008d577d6 drm/amdgpu: add the UVD 7.0 register headers 
These are the Unifed Video Decoder registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:28 -04:00
Alex Deucher
893f25540e drm/amdgpu: add THM 9.0 register headers 
These are the THerMal control registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:27 -04:00
Alex Deucher
63d311d9b4 drm/amdgpu: add SMUIO 9.0 register headers 
These are the System Managment Unit IO registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:26 -04:00
Alex Deucher
456f97704f drm/amdgpu: add SDMA 4.0 register headers 
These are the System DMA register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:26 -04:00
Alex Deucher
5a8288c0f9 drm/amdgpu: add OSSSYS 4.0 register headers 
These are the OS Services register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:25 -04:00
Alex Deucher
198b746016 drm/amdgpu: add NBIO 6.1 register headers 
These are the Bus IO registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:24 -04:00
Alex Deucher
61e04478b2 drm/amdgpu: add NBIF 6.1 register headers 
These are the Bus InterFace registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:23 -04:00
Alex Deucher
3ec127a075 drm/amdgpu: add MP 9.0 register headers 
MP is the system management controller on vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:23 -04:00
Alex Deucher
68c7d13052 drm/amdgpu: add the MMHUB 1.0 register headers 
Add the MultiMedia Hub registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:22 -04:00
Alex Deucher
bcfb47cdd7 drm/amdgpu: add the HDP 4.0 register headers 
These are the Host Data Path registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:21 -04:00
Alex Deucher
5585476e44 drm/amdgpu: add the GC 9.0 register headers 
Add the Graphics Core register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:21 -04:00
Alex Deucher
4adc5ab813 drm/amdgpu: Add the DCE 12.0 register headers 
These are the register headers for the Display
and Composition Engine on vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:20 -04:00
Alex Deucher
7fee1fd93b drm/amdgpu: Add ATHUB 1.0 register headers 
ATHUB is part of the memory controller on soc15 asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:19 -04:00
Alex Deucher
733acf561e drm/amdgpu: add vega10_enum.h 
This adds the register bitfield enums for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:19 -04:00
Alex Deucher
1fd1cc5640 drm/amdgpu: add soc15ip.h 
This header defines the IP layout for soc15 based SoCs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:18 -04:00
Alex Deucher
a5bde2f964 drm/amdgpu: add basic support for atomfirmware.h (v3) 
This adds basic support for asics that use atomfirmware.h
to define their vbios tables.

v2: rebase
v3: squash in num scratch reg fix

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:17 -04:00
Alex Deucher
43bf11bd92 drm/amdgpu: move atom scratch setup into amdgpu_atombios.c 
There will be a slightly different version for atomfirmware.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:17 -04:00
Alex Deucher
0cdd500560 amdgpu: detect if we are using atomfirmware or atombios for vbios (v2) 
Supposedly atomfirmware rom header is 3.3 atombios is 1.1.

v2: rebased on newer kernel

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:16 -04:00
Alex Deucher
1fadf42ed5 drm/amdgpu: add the new atomfirmware interface header 
soc15 asics have a new vbios interface.  These headers
define that interface.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:15 -04:00
Nicolai Hähnle
f34678187a drm/amdgpu: add optional fence out-parameter to amdgpu_vm_clear_freed 
We will add the fence to freed buffer objects in a later commit, to ensure
that the underlying memory can only be re-used after all references in
page tables have been cleared.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:15 -04:00
Eric Huang
923d26db85 drm/amd/powerplay: restore disabling power containment on Fiji (v2) 
Power containment will degrade performance in some compute tests.
Restore disabling it as before code refining in powerplay.

v2: only in the compute profile

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:14 -04:00
Alex Deucher
a2140e00e0 drm/amdgpu/gfx8: further KIQ parameter cleanup 
The ring structure already has what we need.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:13 -04:00
Alex Deucher
345346108b drm/amdgpu/gfx8: store the eop gpu addr in the ring structure 
Avoids passing around additional parameters during setup.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:13 -04:00
Alex Deucher
015c23600a drm/amdgpu/gfx8: reduce the functon params for mpq setup 
Everything we need is in the ring structure.  No need to
pass all the bits explicitly.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:12 -04:00
Alex Deucher
f2effd49e7 drm/amdgpu/gfx8: reserve kiq eop object before unmapping it 
It's required.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:12 -04:00
Alex Deucher
0104cf2536 drm/amdgpu/gfx8: fold loops in kiq_resume() 
No need to loop through the compute queues twice.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:11 -04:00
Alex Deucher
2e263c824a drm/amdgpu/gfx8: test KIQ before compute rings 
If KIQ isn't working, the compute rings won't work either.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:10 -04:00
Alex Deucher
6a6f380f07 drm/amdgpu/gfx8: reserve mqd objects before mapping them 
It's required.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:10 -04:00
Alex Deucher
0875a24296 drm/amdgpu/gfx8: rename some functions 
To better match where they are used.  Called from sw_init
and sw_fini.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:09 -04:00
Alex Deucher
b0ac2a32ad drm/amdgpu/gfx8: whitespace cleanup 
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:08 -04:00
Rex Zhu
0d52c6a13e drm/amdgpu: load mc firware in driver for Polaris. 
load mc ucode in driver if VBIOS not loaded
a full version of MC ucode,

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: jimqu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:08 -04:00
Chunming Zhou
aacbbc8bc1 drm/amdgpu: fix duplicated code 
it could come from branch merge.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:07 -04:00
Rex Zhu
739e9fffde drm/amdgpu: enable gfx/system/vce clockgating on Polars12. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:06 -04:00
Rex Zhu
1c622002b1 drm/amd/powerplay: add a new register define for APU in VI. 
the ixcurrent_pg_status addr is different between APU and DGPU.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:06 -04:00
Eric Huang
170d6e94e5 drm/amdgpu: enable GFX/UVD/VCE PG for Bristol 
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:05 -04:00
Tom St Denis
d1aff8ec49 drm/amd/amdgpu: Set VCE/UVD off during late init 
Forces VCE/UVD off during late init to ensure they're powered off
correctly during boot.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:05 -04:00
Colin Ian King
f917c2ad92 drm/amdgpu: remove redundant outer loop and remove commented out code 
The outer loop is redundant and can be removed as it is doing nothing
useful. Also remove some commented out code that is not being used.

Detected by CoverityScan, CID#1402073

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:04 -04:00
Chunming Zhou
153de9dff9 drm/amd/sched: revise priority number 
big number is to high priority.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:03 -04:00
Alex Deucher
8eafd505db drm/amdgpu: bump version for PRT support 
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:03 -04:00
Junwei Zhang
27f6d61036 drm/amdgpu: fix before and after mapping judgement for replace mapping 
If the before mapping is 1 page size, so its start and last will be same.
Thus below condition will become false, then to free the before mapping.
   > if (before->it.start != before->it.last)
But in this case, we need the before mapping of 1 page size.
So does after mapping.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:02 -04:00
Christian König
80f95c579d drm/amdgpu: add a VM mapping replace operation v2 
Add a new operation to replace mappings in a VM with a new one.

v2: Fix Jerry's comment, separate out clear operation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:01 -04:00
Christian König
dc54d3d174 drm/amdgpu: implement AMDGPU_VA_OP_CLEAR v2 
A new VM operation to remove all mappings in a range.

v2: limit unmapped area as noted by Jerry

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:01 -04:00
Christian König
663e4577a5 drm/amdgpu: separate page table allocation from mapping 
This makes it easier to implement a replace operation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:54:00 -04:00
Christian König
4388fc2ab0 drm/amdgpu: make set_prt callback optional and fix error handling 
PRT support is completely implemented now and we left it
turned on accidentially in the error path.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-29 23:53:59 -04:00