The I2C block in the Ux500 uses internal pull-ups on the
SoC, in fact it has to: in HS mode, the I2C block will need
to autonomously take control over the pull-up line to do
its job. This can be clearly seen from the SoC manual which
states that the silicon has a line named "en_cspu_hs" which
enables current source pull-up for high speed mode. Another
hint is that the vendor code tree never enabled the pull
up on these lines, despite being deployed on boards that
lack external pull-up resistors.
Tested on the Ux500 reference designs without any problems.
Cc: Stephan Gerhold <stephan@gerhold.net>
Reported-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191126123116.56244-1-linus.walleij@linaro.org
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Tested-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Ux500 device tree uses "arm,rtc-pl031" as compatible for PL031.
All other boards in Linux describe it using "arm,pl031" instead.
This works because the compatible is not actually used in Linux:
AMBA devices get probed based on "arm,primecell" and their peripheral ID.
Nevertheless, some other projects (e.g. U-Boot) rely on the compatible
to probe the device with the correct driver. Those will look for
"arm,pl031" instead of "arm,rtc-pl031", preventing the RTC from being
probed.
Change it to "arm,pl031" to match all other boards.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191124205110.48031-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The "soc" node in the Ux500 device tree does not need any special
handling - it is just a simple I/O bus that can be accessed without
additional configuration.
Therefore we can additionally describe it as compatible with "simple-bus".
This can be used by platforms to probe devices under the soc node without
special handling for our custom "stericsson,db8500" compatible
(e.g. in U-Boot).
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191124195728.32226-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Now that we have aliases for I2C and SPI in ste-dbx5x0.dtsi,
it does not make much sense to keep only the aliases for UART
separately in each board device tree.
Considering that all boards set the same aliases for the serial
ports there is no reason to keep them separated either.
Move them to ste-dbx5x0.dtsi and remove the aliases from the
board-specific device tree parts.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125170428.76069-3-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Now that we disable the I2C/SPI buses by default, is is even more
important to assign aliases to the I2C/SPI device nodes.
Otherwise, enabling/disabling one of them will potentially change
all device IDs, e.g. i2c2 will be named i2c-0 if it is the only
enabled I2C bus.
Add aliases for the I2C and SPI buses to avoid this.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125170428.76069-2-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
At the moment, all 5 I2C and 6 SPI buses are probed and exposed
to user-space by default - even if they are not muxed to any pins
on the board. This means that user-space sees an I2C/SPI bus that
cannot be actually used properly.
In some cases this was used to put the corresponding pins into
a low power sleep mode - but even then the pins first need to be
configured by the board-specific device tree part.
Avoid exposing unconfigured devices to user-space by disabling
the I2C/SPI buses by default. Enable them in the board device trees
when needed.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125170428.76069-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
SDI0/SDI1 can be used in configurations where some of the pins
(e.g. direction control) are not used. The pinctrl driver has
separate pin groups for them.
Add new pin configurations for:
- mc0_a_2: like mc0_a_1, but without CMDDIR/DAT0DIR/DAT2DIR
- mc1_a_2: like mc1_a_1, but without FBCLK
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-3-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some components (e.g. SDI, I2C) can be used with different pin assignments.
Before we can add the alternative configurations, we need to rename the
current configurations to more generic names.
Each pin configuration usually configures one specific pin group.
Therefore we rename the configurations to use the pin group as name.
Make up for the slightly longer names by removing the "_mode" suffix.
Rename all existing uses to use the new labels.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-2-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
All existing Ux500 boards make use of ste-href-family-pinctrl.dtsi,
which contains shared pin configurations for UART, I2C and SDI.
Most of these can be also used for devices not based on HREF.
Move the generic pin configs into a new device tree include
"ste-dbx5x0-pinctrl.dtsi". There is no functional change (yet),
as a next step we will rename the pin configs to use more generic
names.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the IIO channels for the GPADC after converting it
to using the standard IIO ADC bindings and moving the driver
over to the IIO subsystem. We also add IIO hwmon standard
driver node to support reading channels in a standard manner.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Replace all "@" and "_" by "-" in pinmux groups for stm32f7 family.
This avoid errors when using yaml to check the bindings.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Replace all "@" and "_" by "-" in pinmux groups for stm32f4 family.
This avoid errors when using yaml to check the bindings.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit adds security (cryp1) IP to stm32mp157c ED1 board by including
stm32mp15xc.dtsi file.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
To handle STM32MP15 SOCs diversity, some updates have to been done.
This commit mainly adapt dk1 board to include the correct package and the
correct SOC version. A new file has been created to factorize common parts.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit creates a new file to manage security diversity on STM32MP15x
SOCs. On STM32MP15xY, "Y" gives information:
-Y = A means no cryp IP and no secure boot.
-Y = C means cryp IP + secure boot.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
In order to cover the STM32MP15 SOCs family this commit updates pinctrl
file names (group definition and packages files).
This family includes: STM32MP151, STM32MP153 and STM32MP157.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit modifies stm32mp157 pinctrl files to better manage STM32MP15xx
SOCs diversity. Pin controller and gpio controller are moved to common SOC
dtsi file. Only pin groups remain in the main pinctrl dtsi file.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add ADC support to stm32mp157c-ed1 board.
Following ADC signals are dedicated for analog and routed to connectors:
- ADC1/2 in0 (ANA0)
- ADC1/2 in1 (ANA1)
- ADC1 in6 (PF12)
Configure ADC1 with these signals. But keep it disabled by default, so
PF12 can be used as gpio by default.
Add VDD and VDDA supplies to ADC on stm32mp157c-ed1 board. This allows to
get full ADC analog performances in case VDDA is below 2.7V (not the case
by default).
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
On STM32MP1 EVAL and DISCOVERY boards, the SDMMC3 internal peripheral
can be used through the GPIO extension connector. The sdmmc3 node is then
added in the boards DT files, and the required pins are also added.
The node status is disabled as there is no device connected by default.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
On STM32MP157C-ED1, the eMMC is connected on instance 2 of SDMMC
peripheral. The sdmmc2 node is then added in the board DT file, as well as
the pins nodes in the pinctrl file.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
The STM32MP157 SoC series includes 3 instances of the SDMMC peripheral.
The sdmmc2 and sdmmc3 nodes are added in STM32MP157 SoC DT file.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add PWM support on stm32mp157a-dk1 board. There are several timers channels
made available on GPIO expansion and arduino connectors:
- Add PWM and trigger support (these timers can also be used as trigger
for ADC).
It's easier then to configure them all. But keep them disabled by default,
so the pins are kept in their initial state to lower power consumption.
This way they can also be used as GPIO.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add all PWM pinctrl definitions that can be used on stm32mp157a-dk1 board.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
The power button was only producing irqs, but no key events,
Forced power down with long key press works, so probably
only a short spike arrives at the SoC.
Further investigation shows that LDORTC2 is off after boot
of the vendor kernel. LDORTC2 is shared with a GPIO at the pmic
which probably transfers the button press to the SoC.
That regulator off at boot, so "regulator-boot-on" is definitively
wrong. So remove that.
Reported-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Fixes: c100ea86e6 ("ARM: dts: add Netronix E60K02 board common file")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1
have interrupt lines connected to the shared IRQ2_B LS1021A pin.
Switching to interrupts offloads the PHY library from the task of
polling the MDIO status and AN registers (1, 4, 5) every second.
Unfortunately, the BCM5464R quad PHY connected to the switch does not
appear to have an interrupt line routed to the SoC.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds a node describing the six external interrupt lines IRQ0-IRQ5
with configurable polarity.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The internal usbphy of usbhost port1 is only full-speed capable.
We set this limitation in the dtsi.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The usb port represented by &usbhost1 uses an USB phy internal to the
SoC. We add the phy_type to the base dtsi so the board dts only have to
overwrite it if they use a different configuration. While at it we also
pin the usbhost port to host mode.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The following build warning is seen with W=1:
DTC arch/arm/boot/dts/imx6sll-kobo-clarahd.dtb
arch/arm/boot/dts/e60k02.dtsi:51.9-53.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
Pass the memory unit address to fix the problem.
While at it, also pass 'device_type = "memory"', which is recommended
for memory nodes.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The device is almost identical to the Kobo Clara HD. The only
spotted difference is the SoC. It contains an imx6sl
instead of an imx6sll.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i.MX7D SDB Rev-A board should use its own board compatible
string instead of default i.MX7D SDB board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i.MX6SX SDB Rev-A board should use its own board compatible
string instead of default i.MX6SX SDB board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The LCD used with the imx6q-logicpd board has an integrated
ili2117a touch controller connected to i2c1.
This patch adds the node to enable this feature.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Without this "jedec,spi-nor" compatible property, probing of the SPI NOR
does not work on the NXP i.MX6ULL EVK. Fix this by adding this
compatible property to the DT.
Fixes: 7d77b8505a ("ARM: dts: imx6ull: fix the imx6ull-14x14-evk configuration")
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This pull request contains the second batch of changes for Broadcom
ARM-based SoCs, please pull the following:
- Nicolas declares a CMA area within the first 1GB of DRAM in order for
it to be guaranteed to reside there, otherwise ARM64's memory
initialization will pick up a CMA area within ZONE_DMA32
- Stefan adds the Device Tree node for the built-in Ethernet controller
(GENET) on the Raspberry Pi 4 model B board
* tag 'arm-soc/for-5.5/devicetree-part2' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm2711-rpi-4: Enable GENET support
ARM: dts: bcm2711: force CMA into first GB of memory
Link: https://lore.kernel.org/r/20191118182931.11884-1-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
