xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
680,728 Commits 2 Branches 0 Tags
00f06b246a3056bbaa901a90a5a93c9f81ab8e36
Commit Graph

680728 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
John Brooks
00f06b246a drm/amdgpu: Throttle visible VRAM moves separately 
The BO move throttling code is designed to allow VRAM to fill quickly if it
is relatively empty. However, this does not take into account situations
where the visible VRAM is smaller than total VRAM, and total VRAM may not
be close to full but the visible VRAM segment is under pressure. In such
situations, visible VRAM would experience unrestricted swapping and
performance would drop.

Add a separate counter specifically for moves involving visible VRAM, and
check it before moving BOs there.

v2: Only perform calculations for separate counter if visible VRAM is
    smaller than total VRAM. (Michel Dänzer)
v3: [Michel Dänzer]
* Use BO's location rather than the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
  flag to determine whether to account a move for visible VRAM in most
  cases.
* Use a single

	if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {

  block in amdgpu_cs_get_threshold_for_moves.

Fixes: 95844d20ae (drm/amdgpu: throttle buffer migrations at CS using a fixed MBps limit (v2))
Signed-off-by: John Brooks <john@fastquake.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:33 -04:00
John Brooks
218b5dcde4 drm/amdgpu: Add vis_vramlimit module parameter 
Allow specifying a limit on visible VRAM via a module parameter. This is
helpful for testing performance under visible VRAM pressure.

v2: Add cast to 64-bit (Christian König)

Signed-off-by: John Brooks <john@fastquake.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:32 -04:00
Christian König
f9321cc440 drm/amdgpu: change gartsize default to 256MB 
Limit the default GART size and save a lot of VRAM.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:31 -04:00
Christian König
36d3837266 drm/amdgpu: add new gttsize module parameter v2 
This allows setting the gtt size independent of the gart size.

v2: fix copy and paste typo

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:31 -04:00
Christian König
bb84284e10 drm/amdgpu: limit the GTT manager address space 
We should only cover the GART size with the GTT manager.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:30 -04:00
Christian König
6f02a69648 drm/amdgpu: consistent name all GART related parts 
Rename symbols from gtt_ to gart_ as appropriate.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:30 -04:00
Christian König
ed21c047e9 drm/amdgpu: remove gtt_base_align handling 
Not used any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:29 -04:00
Christian König
3490bdb537 drm/amdgpu: move GART struct and function into amdgpu_gart.h v2 
No functional change, just cleanup.

v2: rebased, keep gart name.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:28 -04:00
Alex Deucher
70d17a25da drm/amdgpu: check scratch registers to see if we need post (v2) 
Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.

v2: The scratch register is only used on CIK+

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:28 -04:00
Alex Deucher
833fa075b8 drm/amdgpu/soc15: init nbio registers for vega10 
Call nbio init registers on hw_init to set up any
nbio registers that need initialization at hw init time.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:27 -04:00
Alex Deucher
12097c6d67 drm/amdgpu: add nbio 6.1 register init function 
Used for nbio registers that need to be initialized.  Currently
only used for a golden setting that got missed on some boards.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:27 -04:00
Evan Quan
9b7b8154cd drm/amd/powerplay: added didt support for vega10 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:26 -04:00
Evan Quan
209ee27e9b drm/amd/powerplay: added grbm_idx_mutex lock/unlock to cgs v2 
- v2: rename param 'en' as 'lock'

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:25 -04:00
Evan Quan
c62a59d0c8 drm/amd/powerplay: added support for new se_cac_idx APIs to cgs 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:25 -04:00
Evan Quan
2f11fb0287 drm/amd/powerplay: added soc15 support for new se_cac_idx APIs 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:24 -04:00
Evan Quan
16abb5d206 drm/amd/powerplay: added new se_cac_idx r/w APIs v2 
- v2: added missing spinlock init

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:24 -04:00
Evan Quan
560460f282 drm/amd/powerplay: added index gc cac read/write apis for vega10 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:23 -04:00
Christian König
09628c3f68 drm/amdgpu: use TTM values instead of MC values for the info queries 
Use the TTM values instead of the hardware config here.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:23 -04:00
Christian König
935eefb312 drm/amdgpu: remove maximum BO size limitation v2 
We can finally remove this now.

v2: remove now unused max_size variable as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:22 -04:00
Christian König
5e7e83963f drm/amdgpu: stop mapping BOs to GTT 
No need to map BOs to GTT on eviction and intermediate transfers any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:21 -04:00
Christian König
abca90f1c8 drm/amdgpu: use the GTT windows for BO moves v2 
This way we don't need to map the full BO at a time any more.

v2: use fixed windows for src/dst

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:21 -04:00
Christian König
0c2c421e26 drm/amdgpu: add amdgpu_gart_map function v2 
This allows us to write the mapped PTEs into
an IB instead of the table directly.

v2: fix build with debugfs enabled, remove unused assignment

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:20 -04:00
Christian König
cc25188afd drm/amdgpu: reserve the first 2x512 pages of GART 
We want to use them as remap address space.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:20 -04:00
Colin Ian King
606ce3c098 drm/amdgpu: make arrays pctl0_data and pctl1_data static 
The arrays pctl0_data and pctl1_data do not need to be in global scope,
so them both static.

Cleans up sparse warnings:
symbol 'pctl0_data' was not declared. Should it be static?
symbol 'pctl1_data' was not declared. Should it be static?

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:19 -04:00
Alex Deucher
8d6a5230e1 drm/amdgpu/gmc9: get vram width from atom for Raven 
Get it from the system info table.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:18 -04:00
Alex Deucher
21f6bcb6d4 drm/amdgpu/atomfirmware: implement vram_width for APUs 
Implement support using the new atomfirmware system info table.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:18 -04:00
Alex Deucher
6c88555414 drm/amdgpu/atom: fix atom_fw check 
Not all vbios images seem to set the version appropriately.
Switch the check based on asic type instead.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:17 -04:00
Alex Xie
a5d20c405a drm/amdgpu: Free resources of bo_list when idr_alloc fails 
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:17 -04:00
Rex Zhu
74c31c6e61 drm/amd/powerplay: add avfs check for old asics on Vi. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:16 -04:00
Rex Zhu
ce09d8ecb1 drm/amd/powerplay: move VI common AVFS code to smu7_smumgr.c 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:16 -04:00
Rex Zhu
b37afd41a1 drm/amd/powerplay: refine avfs enable code on fiji. 
1. simplify avfs state switch.
2. delete save/restore VFT table functions as not support
   by fiji.
3. implement thermal_avfs_enable funciton.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:15 -04:00
Rex Zhu
bcadae8423 drm/amd/powerplay: fix avfs state update error on polaris. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:14 -04:00
Evan Quan
8882635119 drm/amd/powerplay: fixed wrong data type declaration for ppfeaturemask 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:14 -04:00
Huang Rui
342169c422 drm/amdgpu: set firmware loading type as direct by default for raven 
In previous case, driver can't enable psp via the kernel parameter for raven.
We should open this path and set it as direct by default till psp firmware
loading is workable.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:13 -04:00
Huang Rui
a1952da73f drm/amdgpu: make psp cmd buffer as a reserve memory 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:13 -04:00
Huang Rui
311146c91a drm/amdgpu: fix missed asd bo free when hw_fini 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:12 -04:00
Huang Rui
edc4d3db06 drm/amdgpu: remove superfluous check 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:11 -04:00
Shaoyun Liu
57ea8c7b4d drm/amdgpu: NO KIQ usage on nbio hdp flush routine 
nbio hdp flush routine are called within atomic context.
Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register
since this register has its own VF copy

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:11 -04:00
Shaoyun Liu
c708535e9c drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro define 
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:10 -04:00
Monk Liu
8fdf074f18 drm/amdgpu:fix world switch hang 
for SR-IOV, we must keep the pipeline-sync in the protection
of COND_EXEC, otherwise the command consumed by CPG is not
consistent when world switch triggerd, e.g.:

world switch hit and the IB frame is skipped so the fence
won't signal, thus CP will jump to the next DMAframe's pipeline-sync
command, and it will make CP hang foever.

after pipelin-sync moved into COND_EXEC the consistency can be
guaranteed

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:10 -04:00
Rex Zhu
bdb8cd10b9 drm/amd/powerplay: enable ACG feature on vega10. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:09 -04:00
Rex Zhu
fc3a4fc631 drm/amd/powerplay: add acg support in pptable for vega10 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:08 -04:00
Rex Zhu
3272cfcf73 drm/amd/powerplay: export ACG related smu message for vega10 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:08 -04:00
Rex Zhu
b743750952 drm/amd/powerplay: add avfs profiling_info_v4_2 support on Vega10. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:07 -04:00
Evan Quan
747f6c921d drm/amdgpu: add ACG SMU firmware for other vega10 variants 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:07 -04:00
Evan Quan
a80c929442 drm/amdgpu: drop SMU_DRIVER_IF_VERSION check for some vega10 variants 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:06 -04:00
Ken Wang
47ed4e1c93 drm/amdgpu: add workaround for S3 issues on some vega10 boards 
Certain MC registers need a delay after writing them to properly
update in the init sequence.

Signed-off-by: Ken Wang <Ken.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:06 -04:00
Alex Deucher
4426826c02 drm/amdgpu/atombios: add function for whether we need asic_init 
Check the atom scratch registers to see if asic_init is complete
or not.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:05 -04:00
Alex Deucher
d05da0e24b drm/amdgpu: unify some atombios/atomfirmware scratch reg functions 
Now that we use a pointer to the scratch reg start offset,
most of the functions were duplicated.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:04 -04:00
Alex Deucher
3164cba317 drm/amdgpu/atombios: use bios_scratch_reg_offset for atombios 
Align with the atomfirmware code.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-07-14 11:06:04 -04:00