x86/platform/uv: Update MMIOH references based on new UV5 MMRs
Make modifications to the MMIOH mappings to accommodate changes for UV5. [ Fix W=1 build warnings. ] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Mike Travis <mike.travis@hpe.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Steve Wahl <steve.wahl@hpe.com> Link: https://lkml.kernel.org/r/20201005203929.148656-8-mike.travis@hpe.com
This commit is contained in:
Mike Travis
committed by
Borislav Petkov
Borislav Petkov
parent
1e61f5a95f
commit
ffe2febca4
@@ -226,6 +226,13 @@ static void __init uv_tsc_check_sync(void)
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mark_tsc_unstable("UV BIOS");
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}
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/* Selector for (4|4A|5) structs */
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#define uvxy_field(sname, field, undef) ( \
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is_uv(UV4A) ? sname.s4a.field : \
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is_uv(UV4) ? sname.s4.field : \
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is_uv(UV3) ? sname.s3.field : \
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undef)
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/* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
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#define SMT_LEVEL 0 /* Leaf 0xb SMT level */
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@@ -878,6 +885,7 @@ static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
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}
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enum map_type {map_wb, map_uc};
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static const char * const mt[] = { "WB", "UC" };
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static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
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{
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@@ -889,11 +897,13 @@ static __init void map_high(char *id, unsigned long base, int pshift, int bshift
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pr_info("UV: Map %s_HI base address NULL\n", id);
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return;
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}
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pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
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if (map_type == map_uc)
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init_extra_mapping_uc(paddr, bytes);
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else
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init_extra_mapping_wb(paddr, bytes);
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pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
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id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
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}
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static __init void map_gru_high(int max_pnode)
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@@ -927,52 +937,74 @@ static __init void map_mmr_high(int max_pnode)
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pr_info("UV: MMR disabled\n");
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}
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/* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */
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static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
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{
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unsigned long overlay;
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unsigned long mmr;
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unsigned long base;
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unsigned long nasid_mask;
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unsigned long m_overlay;
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int i, n, shift, m_io, max_io;
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int nasid, lnasid, fi, li;
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char *id;
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/* Arch specific ENUM cases */
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enum mmioh_arch {
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UV2_MMIOH = -1,
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UVY_MMIOH0, UVY_MMIOH1,
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UVX_MMIOH0, UVX_MMIOH1,
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};
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if (index == 0) {
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id = "MMIOH0";
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m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0;
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overlay = uv_read_local_mmr(m_overlay);
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base = overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
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mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
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m_io = (overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK)
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>> UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT;
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shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT;
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n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
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nasid_mask = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK;
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} else {
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id = "MMIOH1";
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m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1;
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overlay = uv_read_local_mmr(m_overlay);
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base = overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
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mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
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m_io = (overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK)
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>> UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT;
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shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT;
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n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
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nasid_mask = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK;
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/* Calculate and Map MMIOH Regions */
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static void __init calc_mmioh_map(enum mmioh_arch index,
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int min_pnode, int max_pnode,
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int shift, unsigned long base, int m_io, int n_io)
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{
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unsigned long mmr, nasid_mask;
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int nasid, min_nasid, max_nasid, lnasid, mapped;
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int i, fi, li, n, max_io;
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char id[8];
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/* One (UV2) mapping */
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if (index == UV2_MMIOH) {
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strncpy(id, "MMIOH", sizeof(id));
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max_io = max_pnode;
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mapped = 0;
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goto map_exit;
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}
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pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
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if (!(overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK)) {
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pr_info("UV: %s disabled\n", id);
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/* small and large MMIOH mappings */
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switch (index) {
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case UVY_MMIOH0:
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mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
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nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
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n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
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min_nasid = min_pnode;
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max_nasid = max_pnode;
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mapped = 1;
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break;
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case UVY_MMIOH1:
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mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
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nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
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n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
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min_nasid = min_pnode;
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max_nasid = max_pnode;
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mapped = 1;
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break;
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case UVX_MMIOH0:
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mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
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nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
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n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
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min_nasid = min_pnode * 2;
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max_nasid = max_pnode * 2;
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mapped = 1;
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break;
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case UVX_MMIOH1:
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mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
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nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
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n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
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min_nasid = min_pnode * 2;
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max_nasid = max_pnode * 2;
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mapped = 1;
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break;
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default:
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pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
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return;
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}
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/* Convert to NASID: */
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min_pnode *= 2;
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max_pnode *= 2;
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max_io = lnasid = fi = li = -1;
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/* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */
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snprintf(id, sizeof(id), "MMIOH%d", index%2);
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max_io = lnasid = fi = li = -1;
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for (i = 0; i < n; i++) {
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unsigned long m_redirect = mmr + i * 8;
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unsigned long redirect = uv_read_local_mmr(m_redirect);
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@@ -982,9 +1014,12 @@ static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
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pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
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id, redirect, m_redirect, nasid);
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/* Invalid NASID: */
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if (nasid < min_pnode || max_pnode < nasid)
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/* Invalid NASID check */
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if (nasid < min_nasid || max_nasid < nasid) {
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pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n",
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__func__, index, min_nasid, max_nasid);
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nasid = -1;
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}
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if (nasid == lnasid) {
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li = i;
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@@ -1007,7 +1042,8 @@ static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
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}
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addr1 = (base << shift) + f * (1ULL << m_io);
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addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
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pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
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pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
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id, fi, li, lnasid, addr1, addr2);
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if (max_io < l)
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max_io = l;
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}
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@@ -1015,43 +1051,83 @@ static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
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lnasid = nasid;
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}
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pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
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map_exit:
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pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
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id, base, shift, m_io, max_io, max_pnode);
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if (max_io >= 0)
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if (max_io >= 0 && !mapped)
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map_high(id, base, shift, m_io, max_io, map_uc);
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}
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static __init void map_mmioh_high(int min_pnode, int max_pnode)
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{
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union uvh_rh_gam_mmioh_overlay_config_u mmioh;
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unsigned long mmr, base;
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int shift, enable, m_io, n_io;
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/* UVY flavor */
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if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
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union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
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union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
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if (is_uv3_hub() || is_uv4_hub()) {
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/* Map both MMIOH regions: */
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map_mmioh_high_uv34(0, min_pnode, max_pnode);
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map_mmioh_high_uv34(1, min_pnode, max_pnode);
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mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
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if (unlikely(mmioh0.s.enable == 0))
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pr_info("UV: MMIOH0 disabled\n");
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else
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calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
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UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
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mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
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mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
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if (unlikely(mmioh1.s.enable == 0))
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pr_info("UV: MMIOH1 disabled\n");
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else
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calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
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UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
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mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
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return;
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}
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/* UVX flavor */
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if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
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union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
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union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
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mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
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if (unlikely(mmioh0.s.enable == 0))
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pr_info("UV: MMIOH0 disabled\n");
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else {
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unsigned long base = uvxy_field(mmioh0, base, 0);
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int m_io = uvxy_field(mmioh0, m_io, 0);
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int n_io = uvxy_field(mmioh0, n_io, 0);
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calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
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UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
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base, m_io, n_io);
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}
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mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
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if (unlikely(mmioh1.s.enable == 0))
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pr_info("UV: MMIOH1 disabled\n");
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else {
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unsigned long base = uvxy_field(mmioh1, base, 0);
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int m_io = uvxy_field(mmioh1, m_io, 0);
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int n_io = uvxy_field(mmioh1, n_io, 0);
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calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
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UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
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base, m_io, n_io);
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}
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return;
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}
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if (is_uv2_hub()) {
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mmr = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG;
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shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT;
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mmioh.v = uv_read_local_mmr(mmr);
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enable = !!mmioh.s2.enable;
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base = mmioh.s2.base;
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m_io = mmioh.s2.m_io;
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n_io = mmioh.s2.n_io;
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/* UV2 flavor */
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if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
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union uvh_rh_gam_mmioh_overlay_config_u mmioh;
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if (enable) {
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max_pnode &= (1 << n_io) - 1;
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pr_info(
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"UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
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base, shift, m_io, n_io, max_pnode);
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map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
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} else {
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mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
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if (unlikely(mmioh.s2.enable == 0))
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pr_info("UV: MMIOH disabled\n");
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}
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else
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calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
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UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
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mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
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return;
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}
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}
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