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clk:aspeed: Fix reset bits for PCI/VGA and PECI

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This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.

Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f8 ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Jae Hyun Yoo
2018-04-26 10:22:32 -07:00
committed by Stephen Boyd
parent dcb899c47d
commit e76e56823a
2 changed files with 3 additions and 3 deletions
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2
include/dt-bindings/clock/aspeed-clock.h
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@@ -45,7 +45,7 @@
#define ASPEED_RESET_JTAG_MASTER 3
#define ASPEED_RESET_MIC 4
#define ASPEED_RESET_PWM 5
#define ASPEED_RESET_PCIVGA 6
#define ASPEED_RESET_PECI 6
#define ASPEED_RESET_I2C 7
#define ASPEED_RESET_AHB 8
#define ASPEED_RESET_CRT1 9