e76e56823a
This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.
1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f8 ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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#ifndef DT_BINDINGS_ASPEED_CLOCK_H
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#define DT_BINDINGS_ASPEED_CLOCK_H
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#define ASPEED_CLK_GATE_ECLK 0
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#define ASPEED_CLK_GATE_GCLK 1
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#define ASPEED_CLK_GATE_MCLK 2
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#define ASPEED_CLK_GATE_VCLK 3
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#define ASPEED_CLK_GATE_BCLK 4
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#define ASPEED_CLK_GATE_DCLK 5
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#define ASPEED_CLK_GATE_REFCLK 6
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#define ASPEED_CLK_GATE_USBPORT2CLK 7
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#define ASPEED_CLK_GATE_LCLK 8
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#define ASPEED_CLK_GATE_USBUHCICLK 9
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#define ASPEED_CLK_GATE_D1CLK 10
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#define ASPEED_CLK_GATE_YCLK 11
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#define ASPEED_CLK_GATE_USBPORT1CLK 12
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#define ASPEED_CLK_GATE_UART1CLK 13
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#define ASPEED_CLK_GATE_UART2CLK 14
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#define ASPEED_CLK_GATE_UART5CLK 15
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#define ASPEED_CLK_GATE_ESPICLK 16
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#define ASPEED_CLK_GATE_MAC1CLK 17
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#define ASPEED_CLK_GATE_MAC2CLK 18
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#define ASPEED_CLK_GATE_RSACLK 19
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#define ASPEED_CLK_GATE_UART3CLK 20
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#define ASPEED_CLK_GATE_UART4CLK 21
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#define ASPEED_CLK_GATE_SDCLKCLK 22
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#define ASPEED_CLK_GATE_LHCCLK 23
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#define ASPEED_CLK_HPLL 24
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#define ASPEED_CLK_AHB 25
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#define ASPEED_CLK_APB 26
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#define ASPEED_CLK_UART 27
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#define ASPEED_CLK_SDIO 28
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#define ASPEED_CLK_ECLK 29
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#define ASPEED_CLK_ECLK_MUX 30
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#define ASPEED_CLK_LHCLK 31
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#define ASPEED_CLK_MAC 32
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#define ASPEED_CLK_BCLK 33
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#define ASPEED_CLK_MPLL 34
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#define ASPEED_RESET_XDMA 0
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#define ASPEED_RESET_MCTP 1
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#define ASPEED_RESET_ADC 2
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#define ASPEED_RESET_JTAG_MASTER 3
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#define ASPEED_RESET_MIC 4
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#define ASPEED_RESET_PWM 5
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#define ASPEED_RESET_PECI 6
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#define ASPEED_RESET_I2C 7
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#define ASPEED_RESET_AHB 8
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#define ASPEED_RESET_CRT1 9
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#endif
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