ath10k: add hw params for shadow register support
wcn3990 supports shadow register for ce write. Add a hw param for shadow register support. Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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committed by
Kalle Valo

parent
20529b33aa
commit
b2e40d7ab8
@@ -90,6 +90,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.shadow_reg_support = false,
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},
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{
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.id = QCA988X_HW_2_0_VERSION,
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@@ -120,6 +121,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA9887_HW_1_0_VERSION,
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@@ -150,6 +152,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA6174_HW_2_1_VERSION,
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@@ -179,6 +182,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA6174_HW_2_1_VERSION,
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@@ -208,6 +212,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA6174_HW_3_0_VERSION,
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@@ -237,6 +242,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA6174_HW_3_2_VERSION,
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@@ -269,6 +275,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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@@ -304,6 +311,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA9984_HW_1_0_DEV_VERSION,
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@@ -344,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA9888_HW_2_0_DEV_VERSION,
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@@ -383,6 +392,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA9377_HW_1_0_DEV_VERSION,
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@@ -412,6 +422,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA9377_HW_1_1_DEV_VERSION,
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@@ -443,6 +454,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = QCA4019_HW_1_0_DEV_VERSION,
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@@ -479,6 +491,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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},
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{
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.id = WCN3990_HW_1_0_DEV_VERSION,
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@@ -500,6 +513,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.target_64bit = true,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
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.per_ce_irq = true,
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.shadow_reg_support = true,
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},
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};
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@@ -1,6 +1,7 @@
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/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
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* Copyright (c) 2018 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@@ -571,6 +572,9 @@ struct ath10k_hw_params {
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/* target supporting per ce IRQ */
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bool per_ce_irq;
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/* target supporting shadow register for ce write */
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bool shadow_reg_support;
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};
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struct htt_rx_desc;
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