spi-mt7621.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  4. //
  5. // Copyright (C) 2011 Sergiy <[email protected]>
  6. // Copyright (C) 2011-2013 Gabor Juhos <[email protected]>
  7. // Copyright (C) 2014-2015 Felix Fietkau <[email protected]>
  8. //
  9. // Some parts are based on spi-orion.c:
  10. // Author: Shadi Ammouri <[email protected]>
  11. // Copyright (C) 2007-2008 Marvell Ltd.
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/of_device.h>
  17. #include <linux/reset.h>
  18. #include <linux/spi/spi.h>
  19. #define DRIVER_NAME "spi-mt7621"
  20. /* in usec */
  21. #define RALINK_SPI_WAIT_MAX_LOOP 2000
  22. /* SPISTAT register bit field */
  23. #define SPISTAT_BUSY BIT(0)
  24. #define MT7621_SPI_TRANS 0x00
  25. #define SPITRANS_BUSY BIT(16)
  26. #define MT7621_SPI_OPCODE 0x04
  27. #define MT7621_SPI_DATA0 0x08
  28. #define MT7621_SPI_DATA4 0x18
  29. #define SPI_CTL_TX_RX_CNT_MASK 0xff
  30. #define SPI_CTL_START BIT(8)
  31. #define MT7621_SPI_MASTER 0x28
  32. #define MASTER_MORE_BUFMODE BIT(2)
  33. #define MASTER_FULL_DUPLEX BIT(10)
  34. #define MASTER_RS_CLK_SEL GENMASK(27, 16)
  35. #define MASTER_RS_CLK_SEL_SHIFT 16
  36. #define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
  37. #define MT7621_SPI_MOREBUF 0x2c
  38. #define MT7621_SPI_POLAR 0x38
  39. #define MT7621_SPI_SPACE 0x3c
  40. #define MT7621_CPHA BIT(5)
  41. #define MT7621_CPOL BIT(4)
  42. #define MT7621_LSB_FIRST BIT(3)
  43. struct mt7621_spi {
  44. struct spi_controller *master;
  45. void __iomem *base;
  46. unsigned int sys_freq;
  47. unsigned int speed;
  48. int pending_write;
  49. };
  50. static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
  51. {
  52. return spi_controller_get_devdata(spi->master);
  53. }
  54. static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
  55. {
  56. return ioread32(rs->base + reg);
  57. }
  58. static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
  59. {
  60. iowrite32(val, rs->base + reg);
  61. }
  62. static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
  63. {
  64. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  65. int cs = spi->chip_select;
  66. u32 polar = 0;
  67. u32 master;
  68. /*
  69. * Select SPI device 7, enable "more buffer mode" and disable
  70. * full-duplex (only half-duplex really works on this chip
  71. * reliably)
  72. */
  73. master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  74. master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
  75. master &= ~MASTER_FULL_DUPLEX;
  76. mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
  77. rs->pending_write = 0;
  78. if (enable)
  79. polar = BIT(cs);
  80. mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
  81. }
  82. static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
  83. {
  84. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  85. u32 rate;
  86. u32 reg;
  87. dev_dbg(&spi->dev, "speed:%u\n", speed);
  88. rate = DIV_ROUND_UP(rs->sys_freq, speed);
  89. dev_dbg(&spi->dev, "rate-1:%u\n", rate);
  90. if (rate > 4097)
  91. return -EINVAL;
  92. if (rate < 2)
  93. rate = 2;
  94. reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  95. reg &= ~MASTER_RS_CLK_SEL;
  96. reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
  97. rs->speed = speed;
  98. reg &= ~MT7621_LSB_FIRST;
  99. if (spi->mode & SPI_LSB_FIRST)
  100. reg |= MT7621_LSB_FIRST;
  101. /*
  102. * This SPI controller seems to be tested on SPI flash only and some
  103. * bits are swizzled under other SPI modes probably due to incorrect
  104. * wiring inside the silicon. Only mode 0 works correctly.
  105. */
  106. reg &= ~(MT7621_CPHA | MT7621_CPOL);
  107. mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
  108. return 0;
  109. }
  110. static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
  111. {
  112. int i;
  113. for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
  114. u32 status;
  115. status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  116. if ((status & SPITRANS_BUSY) == 0)
  117. return 0;
  118. cpu_relax();
  119. udelay(1);
  120. }
  121. return -ETIMEDOUT;
  122. }
  123. static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
  124. int rx_len, u8 *buf)
  125. {
  126. int tx_len;
  127. /*
  128. * Combine with any pending write, and perform one or more half-duplex
  129. * transactions reading 'len' bytes. Data to be written is already in
  130. * MT7621_SPI_DATA.
  131. */
  132. tx_len = rs->pending_write;
  133. rs->pending_write = 0;
  134. while (rx_len || tx_len) {
  135. int i;
  136. u32 val = (min(tx_len, 4) * 8) << 24;
  137. int rx = min(rx_len, 32);
  138. if (tx_len > 4)
  139. val |= (tx_len - 4) * 8;
  140. val |= (rx * 8) << 12;
  141. mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
  142. tx_len = 0;
  143. val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  144. val |= SPI_CTL_START;
  145. mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
  146. mt7621_spi_wait_till_ready(rs);
  147. for (i = 0; i < rx; i++) {
  148. if ((i % 4) == 0)
  149. val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
  150. *buf++ = val & 0xff;
  151. val >>= 8;
  152. }
  153. rx_len -= i;
  154. }
  155. }
  156. static inline void mt7621_spi_flush(struct mt7621_spi *rs)
  157. {
  158. mt7621_spi_read_half_duplex(rs, 0, NULL);
  159. }
  160. static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
  161. int tx_len, const u8 *buf)
  162. {
  163. int len = rs->pending_write;
  164. int val = 0;
  165. if (len & 3) {
  166. val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
  167. if (len < 4) {
  168. val <<= (4 - len) * 8;
  169. val = swab32(val);
  170. }
  171. }
  172. while (tx_len > 0) {
  173. if (len >= 36) {
  174. rs->pending_write = len;
  175. mt7621_spi_flush(rs);
  176. len = 0;
  177. }
  178. val |= *buf++ << (8 * (len & 3));
  179. len++;
  180. if ((len & 3) == 0) {
  181. if (len == 4)
  182. /* The byte-order of the opcode is weird! */
  183. val = swab32(val);
  184. mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
  185. val = 0;
  186. }
  187. tx_len -= 1;
  188. }
  189. if (len & 3) {
  190. if (len < 4) {
  191. val = swab32(val);
  192. val >>= (4 - len) * 8;
  193. }
  194. mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
  195. }
  196. rs->pending_write = len;
  197. }
  198. static int mt7621_spi_transfer_one_message(struct spi_controller *master,
  199. struct spi_message *m)
  200. {
  201. struct mt7621_spi *rs = spi_controller_get_devdata(master);
  202. struct spi_device *spi = m->spi;
  203. unsigned int speed = spi->max_speed_hz;
  204. struct spi_transfer *t = NULL;
  205. int status = 0;
  206. mt7621_spi_wait_till_ready(rs);
  207. list_for_each_entry(t, &m->transfers, transfer_list)
  208. if (t->speed_hz < speed)
  209. speed = t->speed_hz;
  210. if (mt7621_spi_prepare(spi, speed)) {
  211. status = -EIO;
  212. goto msg_done;
  213. }
  214. /* Assert CS */
  215. mt7621_spi_set_cs(spi, 1);
  216. m->actual_length = 0;
  217. list_for_each_entry(t, &m->transfers, transfer_list) {
  218. if ((t->rx_buf) && (t->tx_buf)) {
  219. /*
  220. * This controller will shift some extra data out
  221. * of spi_opcode if (mosi_bit_cnt > 0) &&
  222. * (cmd_bit_cnt == 0). So the claimed full-duplex
  223. * support is broken since we have no way to read
  224. * the MISO value during that bit.
  225. */
  226. status = -EIO;
  227. goto msg_done;
  228. } else if (t->rx_buf) {
  229. mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
  230. } else if (t->tx_buf) {
  231. mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
  232. }
  233. m->actual_length += t->len;
  234. }
  235. /* Flush data and deassert CS */
  236. mt7621_spi_flush(rs);
  237. mt7621_spi_set_cs(spi, 0);
  238. msg_done:
  239. m->status = status;
  240. spi_finalize_current_message(master);
  241. return 0;
  242. }
  243. static int mt7621_spi_setup(struct spi_device *spi)
  244. {
  245. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  246. if ((spi->max_speed_hz == 0) ||
  247. (spi->max_speed_hz > (rs->sys_freq / 2)))
  248. spi->max_speed_hz = rs->sys_freq / 2;
  249. if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
  250. dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
  251. spi->max_speed_hz);
  252. return -EINVAL;
  253. }
  254. return 0;
  255. }
  256. static const struct of_device_id mt7621_spi_match[] = {
  257. { .compatible = "ralink,mt7621-spi" },
  258. {},
  259. };
  260. MODULE_DEVICE_TABLE(of, mt7621_spi_match);
  261. static int mt7621_spi_probe(struct platform_device *pdev)
  262. {
  263. const struct of_device_id *match;
  264. struct spi_controller *master;
  265. struct mt7621_spi *rs;
  266. void __iomem *base;
  267. struct clk *clk;
  268. int ret;
  269. match = of_match_device(mt7621_spi_match, &pdev->dev);
  270. if (!match)
  271. return -EINVAL;
  272. base = devm_platform_ioremap_resource(pdev, 0);
  273. if (IS_ERR(base))
  274. return PTR_ERR(base);
  275. clk = devm_clk_get_enabled(&pdev->dev, NULL);
  276. if (IS_ERR(clk))
  277. return dev_err_probe(&pdev->dev, PTR_ERR(clk),
  278. "unable to get SYS clock\n");
  279. master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
  280. if (!master) {
  281. dev_info(&pdev->dev, "master allocation failed\n");
  282. return -ENOMEM;
  283. }
  284. master->mode_bits = SPI_LSB_FIRST;
  285. master->flags = SPI_CONTROLLER_HALF_DUPLEX;
  286. master->setup = mt7621_spi_setup;
  287. master->transfer_one_message = mt7621_spi_transfer_one_message;
  288. master->bits_per_word_mask = SPI_BPW_MASK(8);
  289. master->dev.of_node = pdev->dev.of_node;
  290. master->num_chipselect = 2;
  291. dev_set_drvdata(&pdev->dev, master);
  292. rs = spi_controller_get_devdata(master);
  293. rs->base = base;
  294. rs->master = master;
  295. rs->sys_freq = clk_get_rate(clk);
  296. rs->pending_write = 0;
  297. dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
  298. ret = device_reset(&pdev->dev);
  299. if (ret) {
  300. dev_err(&pdev->dev, "SPI reset failed!\n");
  301. return ret;
  302. }
  303. return devm_spi_register_controller(&pdev->dev, master);
  304. }
  305. MODULE_ALIAS("platform:" DRIVER_NAME);
  306. static struct platform_driver mt7621_spi_driver = {
  307. .driver = {
  308. .name = DRIVER_NAME,
  309. .of_match_table = mt7621_spi_match,
  310. },
  311. .probe = mt7621_spi_probe,
  312. };
  313. module_platform_driver(mt7621_spi_driver);
  314. MODULE_DESCRIPTION("MT7621 SPI driver");
  315. MODULE_AUTHOR("Felix Fietkau <[email protected]>");
  316. MODULE_LICENSE("GPL");