pwm-sl28cpld.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * sl28cpld PWM driver
  4. *
  5. * Copyright (c) 2020 Michael Walle <[email protected]>
  6. *
  7. * There is no public datasheet available for this PWM core. But it is easy
  8. * enough to be briefly explained. It consists of one 8-bit counter. The PWM
  9. * supports four distinct frequencies by selecting when to reset the counter.
  10. * With the prescaler setting you can select which bit of the counter is used
  11. * to reset it. This implies that the higher the frequency the less remaining
  12. * bits are available for the actual counter.
  13. *
  14. * Let cnt[7:0] be the counter, clocked at 32kHz:
  15. * +-----------+--------+--------------+-----------+---------------+
  16. * | prescaler | reset | counter bits | frequency | period length |
  17. * +-----------+--------+--------------+-----------+---------------+
  18. * | 0 | cnt[7] | cnt[6:0] | 250 Hz | 4000000 ns |
  19. * | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns |
  20. * | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns |
  21. * | 3 | cnt[4] | cnt[3:0] | 2 kHz | 500000 ns |
  22. * +-----------+--------+--------------+-----------+---------------+
  23. *
  24. * Limitations:
  25. * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
  26. * - The hardware cannot atomically set the prescaler and the counter value,
  27. * which might lead to glitches and inconsistent states if a write fails.
  28. * - The counter is not reset if you switch the prescaler which leads
  29. * to glitches, too.
  30. * - The duty cycle will switch immediately and not after a complete cycle.
  31. * - Depending on the actual implementation, disabling the PWM might have
  32. * side effects. For example, if the output pin is shared with a GPIO pin
  33. * it will automatically switch back to GPIO mode.
  34. */
  35. #include <linux/bitfield.h>
  36. #include <linux/kernel.h>
  37. #include <linux/mod_devicetable.h>
  38. #include <linux/module.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/pwm.h>
  41. #include <linux/regmap.h>
  42. /*
  43. * PWM timer block registers.
  44. */
  45. #define SL28CPLD_PWM_CTRL 0x00
  46. #define SL28CPLD_PWM_CTRL_ENABLE BIT(7)
  47. #define SL28CPLD_PWM_CTRL_PRESCALER_MASK GENMASK(1, 0)
  48. #define SL28CPLD_PWM_CYCLE 0x01
  49. #define SL28CPLD_PWM_CYCLE_MAX GENMASK(6, 0)
  50. #define SL28CPLD_PWM_CLK 32000 /* 32 kHz */
  51. #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler) (1 << (7 - (prescaler)))
  52. #define SL28CPLD_PWM_PERIOD(prescaler) \
  53. (NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler))
  54. /*
  55. * We calculate the duty cycle like this:
  56. * duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle
  57. *
  58. * With
  59. * max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
  60. * max_duty_cycle = 1 << (7 - prescaler)
  61. * this then simplifies to:
  62. * duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC
  63. * = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg
  64. *
  65. * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing
  66. * precision by doing the divison first.
  67. */
  68. #define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \
  69. (NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg))
  70. #define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \
  71. (DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK))
  72. #define sl28cpld_pwm_read(priv, reg, val) \
  73. regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
  74. #define sl28cpld_pwm_write(priv, reg, val) \
  75. regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
  76. struct sl28cpld_pwm {
  77. struct pwm_chip pwm_chip;
  78. struct regmap *regmap;
  79. u32 offset;
  80. };
  81. #define sl28cpld_pwm_from_chip(_chip) \
  82. container_of(_chip, struct sl28cpld_pwm, pwm_chip)
  83. static int sl28cpld_pwm_get_state(struct pwm_chip *chip,
  84. struct pwm_device *pwm,
  85. struct pwm_state *state)
  86. {
  87. struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
  88. unsigned int reg;
  89. int prescaler;
  90. sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, &reg);
  91. state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;
  92. prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg);
  93. state->period = SL28CPLD_PWM_PERIOD(prescaler);
  94. sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, &reg);
  95. state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);
  96. state->polarity = PWM_POLARITY_NORMAL;
  97. /*
  98. * Sanitize values for the PWM core. Depending on the prescaler it
  99. * might happen that we calculate a duty_cycle greater than the actual
  100. * period. This might happen if someone (e.g. the bootloader) sets an
  101. * invalid combination of values. The behavior of the hardware is
  102. * undefined in this case. But we need to report sane values back to
  103. * the PWM core.
  104. */
  105. state->duty_cycle = min(state->duty_cycle, state->period);
  106. return 0;
  107. }
  108. static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  109. const struct pwm_state *state)
  110. {
  111. struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
  112. unsigned int cycle, prescaler;
  113. bool write_duty_cycle_first;
  114. int ret;
  115. u8 ctrl;
  116. /* Polarity inversion is not supported */
  117. if (state->polarity != PWM_POLARITY_NORMAL)
  118. return -EINVAL;
  119. /*
  120. * Calculate the prescaler. Pick the biggest period that isn't
  121. * bigger than the requested period.
  122. */
  123. prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);
  124. prescaler = order_base_2(prescaler);
  125. if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK))
  126. return -ERANGE;
  127. ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler);
  128. if (state->enabled)
  129. ctrl |= SL28CPLD_PWM_CTRL_ENABLE;
  130. cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);
  131. cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));
  132. /*
  133. * Work around the hardware limitation. See also above. Trap 100% duty
  134. * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't
  135. * care about the frequency because its "all-one" in either case.
  136. *
  137. * We don't need to check the actual prescaler setting, because only
  138. * if the prescaler is 0 we can have this particular value.
  139. */
  140. if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) {
  141. ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK;
  142. ctrl |= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1);
  143. cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1);
  144. }
  145. /*
  146. * To avoid glitches when we switch the prescaler, we have to make sure
  147. * we have a valid duty cycle for the new mode.
  148. *
  149. * Take the current prescaler (or the current period length) into
  150. * account to decide whether we have to write the duty cycle or the new
  151. * prescaler first. If the period length is decreasing we have to
  152. * write the duty cycle first.
  153. */
  154. write_duty_cycle_first = pwm->state.period > state->period;
  155. if (write_duty_cycle_first) {
  156. ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
  157. if (ret)
  158. return ret;
  159. }
  160. ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl);
  161. if (ret)
  162. return ret;
  163. if (!write_duty_cycle_first) {
  164. ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
  165. if (ret)
  166. return ret;
  167. }
  168. return 0;
  169. }
  170. static const struct pwm_ops sl28cpld_pwm_ops = {
  171. .apply = sl28cpld_pwm_apply,
  172. .get_state = sl28cpld_pwm_get_state,
  173. .owner = THIS_MODULE,
  174. };
  175. static int sl28cpld_pwm_probe(struct platform_device *pdev)
  176. {
  177. struct sl28cpld_pwm *priv;
  178. struct pwm_chip *chip;
  179. int ret;
  180. if (!pdev->dev.parent) {
  181. dev_err(&pdev->dev, "no parent device\n");
  182. return -ENODEV;
  183. }
  184. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  185. if (!priv)
  186. return -ENOMEM;
  187. priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
  188. if (!priv->regmap) {
  189. dev_err(&pdev->dev, "could not get parent regmap\n");
  190. return -ENODEV;
  191. }
  192. ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);
  193. if (ret) {
  194. dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",
  195. ERR_PTR(ret));
  196. return -EINVAL;
  197. }
  198. /* Initialize the pwm_chip structure */
  199. chip = &priv->pwm_chip;
  200. chip->dev = &pdev->dev;
  201. chip->ops = &sl28cpld_pwm_ops;
  202. chip->npwm = 1;
  203. ret = devm_pwmchip_add(&pdev->dev, &priv->pwm_chip);
  204. if (ret) {
  205. dev_err(&pdev->dev, "failed to add PWM chip (%pe)",
  206. ERR_PTR(ret));
  207. return ret;
  208. }
  209. return 0;
  210. }
  211. static const struct of_device_id sl28cpld_pwm_of_match[] = {
  212. { .compatible = "kontron,sl28cpld-pwm" },
  213. {}
  214. };
  215. MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match);
  216. static struct platform_driver sl28cpld_pwm_driver = {
  217. .probe = sl28cpld_pwm_probe,
  218. .driver = {
  219. .name = "sl28cpld-pwm",
  220. .of_match_table = sl28cpld_pwm_of_match,
  221. },
  222. };
  223. module_platform_driver(sl28cpld_pwm_driver);
  224. MODULE_DESCRIPTION("sl28cpld PWM Driver");
  225. MODULE_AUTHOR("Michael Walle <[email protected]>");
  226. MODULE_LICENSE("GPL");