pwm-qti-lpg.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #define pr_fmt(fmt) "%s: " fmt, __func__
  7. #include <linux/bitops.h>
  8. #include <linux/device.h>
  9. #include <linux/err.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/mutex.h>
  14. #include <linux/nvmem-consumer.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pwm.h>
  19. #include <linux/qpnp/qpnp-pbs.h>
  20. #include <linux/qpnp/qti-pwm.h>
  21. #include <linux/regmap.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/slab.h>
  24. #include <linux/types.h>
  25. #define REG_SIZE_PER_LPG 0x100
  26. #define LPG_BASE "lpg-base"
  27. #define LUT_BASE "lut-base"
  28. /* LPG module registers */
  29. #define REG_LPG_PERPH_SUBTYPE 0x05
  30. #define REG_LPG_PATTERN_CONFIG 0x40
  31. #define REG_LPG_PWM_SIZE_CLK 0x41
  32. #define REG_LPG_PWM_FREQ_PREDIV_CLK 0x42
  33. #define REG_LPG_PWM_TYPE_CONFIG 0x43
  34. #define REG_LPG_PWM_VALUE_LSB 0x44
  35. #define REG_LPG_PWM_VALUE_MSB 0x45
  36. #define REG_LPG_ENABLE_CONTROL 0x46
  37. #define REG_LPG_PWM_SYNC 0x47
  38. #define REG_LPG_RAMP_STEP_DURATION_LSB 0x50
  39. #define REG_LPG_RAMP_STEP_DURATION_MSB 0x51
  40. #define REG_LPG_PAUSE_HI_MULTIPLIER 0x52
  41. #define REG_LPG_PAUSE_LO_MULTIPLIER 0x54
  42. #define REG_LPG_HI_INDEX 0x56
  43. #define REG_LPG_LO_INDEX 0x57
  44. /* PWM module registers */
  45. #define REG_PWM_STATUS1 0x08
  46. #define FM_MODE_PRESENT BIT(0)
  47. #define REG_PWM_FM_MODE 0x50
  48. #define FM_MODE_ENABLE BIT(7)
  49. /* REG_LPG_PATTERN_CONFIG */
  50. #define LPG_PATTERN_EN_PAUSE_LO BIT(0)
  51. #define LPG_PATTERN_EN_PAUSE_HI BIT(1)
  52. #define LPG_PATTERN_RAMP_TOGGLE BIT(2)
  53. #define LPG_PATTERN_REPEAT BIT(3)
  54. #define LPG_PATTERN_RAMP_LO_TO_HI BIT(4)
  55. /* REG_LPG_PERPH_SUBTYPE */
  56. #define SUBTYPE_PWM 0x0b
  57. #define SUBTYPE_HI_RES_PWM 0x0c
  58. #define SUBTYPE_LPG_LITE 0x11
  59. /* REG_LPG_PWM_SIZE_CLK */
  60. #define LPG_PWM_SIZE_LPG_MASK BIT(4)
  61. #define LPG_PWM_SIZE_PWM_MASK BIT(2)
  62. #define LPG_PWM_SIZE_PWM_HI_RES_MASK GENMASK(6, 4)
  63. #define LPG_PWM_SIZE_LPG_SHIFT 4
  64. #define LPG_PWM_SIZE_PWM_SHIFT 2
  65. #define LPG_PWM_SIZE_PWM_HI_RES_SHIFT 4
  66. #define LPG_PWM_CLK_FREQ_SEL_MASK GENMASK(1, 0)
  67. #define LPG_PWM_HI_RES_CLK_FREQ_SEL_MASK GENMASK(2, 0)
  68. /* REG_LPG_PWM_FREQ_PREDIV_CLK */
  69. #define LPG_PWM_FREQ_PREDIV_MASK GENMASK(6, 5)
  70. #define LPG_PWM_FREQ_PREDIV_SHIFT 5
  71. #define LPG_PWM_FREQ_EXPONENT_MASK GENMASK(2, 0)
  72. /* REG_LPG_PWM_TYPE_CONFIG */
  73. #define LPG_PWM_EN_GLITCH_REMOVAL_MASK BIT(5)
  74. /* REG_LPG_PWM_VALUE_LSB */
  75. #define LPG_PWM_VALUE_LSB_MASK GENMASK(7, 0)
  76. /* REG_LPG_PWM_VALUE_MSB */
  77. #define LPG_PWM_VALUE_MSB_MASK BIT(0)
  78. #define LPG_PWM_HI_RES_VALUE_MSB_MASK GENMASK(7, 0)
  79. /* REG_LPG_ENABLE_CONTROL */
  80. #define LPG_EN_LPG_OUT_BIT BIT(7)
  81. #define LPG_EN_LPG_OUT_SHIFT 7
  82. #define LPG_PWM_SRC_SELECT_MASK BIT(2)
  83. #define LPG_PWM_SRC_SELECT_SHIFT 2
  84. #define LPG_EN_RAMP_GEN_MASK BIT(1)
  85. #define LPG_EN_RAMP_GEN_SHIFT 1
  86. /* REG_LPG_PWM_SYNC */
  87. #define LPG_PWM_VALUE_SYNC BIT(0)
  88. #define NUM_PWM_SIZE 2
  89. #define NUM_PWM_HI_RES_SIZE 8
  90. #define NUM_PWM_CLK 3
  91. #define NUM_PWM_HI_RES_CLK 4
  92. #define NUM_CLK_PREDIV 4
  93. #define NUM_PWM_EXP 8
  94. #define LPG_HI_LO_IDX_MASK GENMASK(5, 0)
  95. /* LUT module registers */
  96. #define REG_LPG_LUT_1_LSB 0x42
  97. #define REG_LPG_LUT_RAMP_CONTROL 0xc8
  98. #define LPG_LUT_VALUE_MSB_MASK BIT(0)
  99. #define LPG_LUT_COUNT_MAX 47
  100. /* LPG config settings in SDAM */
  101. #define SDAM_REG_PBS_SEQ_EN 0x42
  102. #define PBS_SW_TRG_BIT BIT(0)
  103. #define SDAM_REG_RAMP_STEP_DURATION 0x47
  104. #define SDAM_LUT_EN_OFFSET 0x0
  105. #define SDAM_PATTERN_CONFIG_OFFSET 0x1
  106. #define SDAM_END_INDEX_OFFSET 0x3
  107. #define SDAM_START_INDEX_OFFSET 0x4
  108. #define SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET 0x6
  109. #define SDAM_PAUSE_START_MULTIPLIER_OFFSET 0x8
  110. #define SDAM_PAUSE_END_MULTIPLIER_OFFSET 0x9
  111. /* SDAM_REG_LUT_EN */
  112. #define SDAM_LUT_EN_BIT BIT(0)
  113. /* SDAM_REG_PATTERN_CONFIG */
  114. #define SDAM_PATTERN_LOOP_ENABLE BIT(3)
  115. #define SDAM_PATTERN_EN_PAUSE_START BIT(1)
  116. #define SDAM_PATTERN_EN_PAUSE_END BIT(0)
  117. #define SDAM_PAUSE_COUNT_MAX (U8_MAX - 1)
  118. #define SDAM_LUT_COUNT_MAX 64
  119. enum lpg_src {
  120. LUT_PATTERN = 0,
  121. PWM_VALUE,
  122. };
  123. enum ppg_num_nvmems {
  124. PPG_NO_NVMEMS,
  125. PPG_NVMEMS_1, /* A single nvmem for both LUT and LPG channel config */
  126. PPG_NVMEMS_2, /* Two separate nvmems for LUT and LPG channel config */
  127. };
  128. static const int pwm_size[NUM_PWM_SIZE] = {6, 9};
  129. static const int pwm_hi_res_size[NUM_PWM_HI_RES_SIZE] = {8, 9, 10, 11, 12, 13, 14, 15};
  130. static const int clk_freq_hz[NUM_PWM_CLK] = {1024, 32768, 19200000};
  131. static const int clk_freq_hz_hi_res[NUM_PWM_HI_RES_CLK] = {1024, 32768, 19200000, 76800000};
  132. /* clk_period_ns = NSEC_PER_SEC / clk_freq_hz */
  133. static const int clk_period_ns[NUM_PWM_CLK] = {976562, 30517, 52};
  134. static const int clk_period_ns_hi_res[NUM_PWM_HI_RES_CLK] = {976562, 30517, 52, 13};
  135. static const int clk_prediv[NUM_CLK_PREDIV] = {1, 3, 5, 6};
  136. static const int pwm_exponent[NUM_PWM_EXP] = {0, 1, 2, 3, 4, 5, 6, 7};
  137. struct lpg_ramp_config {
  138. u16 step_ms;
  139. u8 pause_hi_count;
  140. u8 pause_lo_count;
  141. u8 hi_idx;
  142. u8 lo_idx;
  143. bool ramp_dir_low_to_hi;
  144. bool pattern_repeat;
  145. bool toggle;
  146. u32 *pattern;
  147. u32 pattern_length;
  148. };
  149. struct lpg_pwm_config {
  150. u32 pwm_size;
  151. u32 pwm_clk;
  152. u32 prediv;
  153. u32 clk_exp;
  154. u16 pwm_value;
  155. u64 best_period_ns;
  156. };
  157. struct qpnp_lpg_lut {
  158. struct qpnp_lpg_chip *chip;
  159. struct mutex lock;
  160. enum ppg_num_nvmems nvmem_count;
  161. u32 reg_base;
  162. u32 *pattern; /* patterns in percentage */
  163. u32 ramp_step_tick_us;
  164. };
  165. struct qpnp_lpg_channel {
  166. struct qpnp_lpg_chip *chip;
  167. struct lpg_pwm_config pwm_config;
  168. struct lpg_ramp_config ramp_config;
  169. enum pwm_output_type output_type;
  170. u32 lpg_idx;
  171. u32 reg_base;
  172. u32 max_pattern_length;
  173. u32 lpg_sdam_base;
  174. u8 src_sel;
  175. u8 subtype;
  176. bool lut_written;
  177. bool enable_pfm;
  178. u64 current_period_ns;
  179. u64 current_duty_ns;
  180. };
  181. struct qpnp_lpg_chip {
  182. struct pwm_chip pwm_chip;
  183. struct regmap *regmap;
  184. struct device *dev;
  185. struct qpnp_lpg_channel *lpgs;
  186. struct qpnp_lpg_lut *lut;
  187. struct mutex bus_lock;
  188. u32 *lpg_group;
  189. struct nvmem_device *lpg_chan_nvmem;
  190. struct nvmem_device *lut_nvmem;
  191. struct device_node *pbs_dev_node;
  192. u32 num_lpgs;
  193. unsigned long pbs_en_bitmap;
  194. bool use_sdam;
  195. };
  196. static int qpnp_lpg_read(struct qpnp_lpg_channel *lpg, u16 addr, u8 *val)
  197. {
  198. int rc;
  199. unsigned int tmp;
  200. mutex_lock(&lpg->chip->bus_lock);
  201. rc = regmap_read(lpg->chip->regmap, lpg->reg_base + addr, &tmp);
  202. if (rc < 0)
  203. dev_err(lpg->chip->dev, "Read addr 0x%x failed, rc=%d\n",
  204. lpg->reg_base + addr, rc);
  205. else
  206. *val = (u8)tmp;
  207. mutex_unlock(&lpg->chip->bus_lock);
  208. return rc;
  209. }
  210. static int qpnp_lpg_write(struct qpnp_lpg_channel *lpg, u16 addr, u8 val)
  211. {
  212. int rc;
  213. mutex_lock(&lpg->chip->bus_lock);
  214. rc = regmap_write(lpg->chip->regmap, lpg->reg_base + addr, val);
  215. if (rc < 0)
  216. dev_err(lpg->chip->dev, "Write addr 0x%x with value 0x%x failed, rc=%d\n",
  217. lpg->reg_base + addr, val, rc);
  218. mutex_unlock(&lpg->chip->bus_lock);
  219. return rc;
  220. }
  221. static int qpnp_lpg_masked_write(struct qpnp_lpg_channel *lpg,
  222. u16 addr, u8 mask, u8 val)
  223. {
  224. int rc;
  225. mutex_lock(&lpg->chip->bus_lock);
  226. rc = regmap_update_bits(lpg->chip->regmap, lpg->reg_base + addr,
  227. mask, val);
  228. if (rc < 0)
  229. dev_err(lpg->chip->dev, "Update addr 0x%x to val 0x%x with mask 0x%x failed, rc=%d\n",
  230. lpg->reg_base + addr, val, mask, rc);
  231. mutex_unlock(&lpg->chip->bus_lock);
  232. return rc;
  233. }
  234. static int qpnp_lut_write(struct qpnp_lpg_lut *lut, u16 addr, u8 val)
  235. {
  236. int rc;
  237. mutex_lock(&lut->chip->bus_lock);
  238. rc = regmap_write(lut->chip->regmap, lut->reg_base + addr, val);
  239. if (rc < 0)
  240. dev_err(lut->chip->dev, "Write addr 0x%x with value %d failed, rc=%d\n",
  241. lut->reg_base + addr, val, rc);
  242. mutex_unlock(&lut->chip->bus_lock);
  243. return rc;
  244. }
  245. static int qpnp_lut_masked_write(struct qpnp_lpg_lut *lut,
  246. u16 addr, u8 mask, u8 val)
  247. {
  248. int rc;
  249. mutex_lock(&lut->chip->bus_lock);
  250. rc = regmap_update_bits(lut->chip->regmap, lut->reg_base + addr,
  251. mask, val);
  252. if (rc < 0)
  253. dev_err(lut->chip->dev, "Update addr 0x%x to val 0x%x with mask 0x%x failed, rc=%d\n",
  254. lut->reg_base + addr, val, mask, rc);
  255. mutex_unlock(&lut->chip->bus_lock);
  256. return rc;
  257. }
  258. static int qpnp_lpg_chan_nvmem_write(struct qpnp_lpg_chip *chip, u16 addr,
  259. u8 val)
  260. {
  261. int rc;
  262. mutex_lock(&chip->bus_lock);
  263. rc = nvmem_device_write(chip->lpg_chan_nvmem, addr, 1, &val);
  264. if (rc < 0)
  265. dev_err(chip->dev, "write SDAM add 0x%x failed, rc=%d\n",
  266. addr, rc);
  267. mutex_unlock(&chip->bus_lock);
  268. return rc > 0 ? 0 : rc;
  269. }
  270. static int qpnp_lpg_sdam_write(struct qpnp_lpg_channel *lpg, u16 addr, u8 val)
  271. {
  272. struct qpnp_lpg_chip *chip = lpg->chip;
  273. int rc;
  274. mutex_lock(&chip->bus_lock);
  275. rc = nvmem_device_write(chip->lpg_chan_nvmem,
  276. lpg->lpg_sdam_base + addr, 1, &val);
  277. if (rc < 0)
  278. dev_err(chip->dev, "write SDAM add 0x%x failed, rc=%d\n",
  279. lpg->lpg_sdam_base + addr, rc);
  280. mutex_unlock(&chip->bus_lock);
  281. return rc > 0 ? 0 : rc;
  282. }
  283. static int qpnp_lpg_sdam_masked_write(struct qpnp_lpg_channel *lpg,
  284. u16 addr, u8 mask, u8 val)
  285. {
  286. int rc;
  287. u8 tmp;
  288. struct qpnp_lpg_chip *chip = lpg->chip;
  289. mutex_lock(&chip->bus_lock);
  290. rc = nvmem_device_read(chip->lpg_chan_nvmem,
  291. lpg->lpg_sdam_base + addr, 1, &tmp);
  292. if (rc < 0) {
  293. dev_err(chip->dev, "Read SDAM addr %d failed, rc=%d\n",
  294. lpg->lpg_sdam_base + addr, rc);
  295. goto unlock;
  296. }
  297. tmp = tmp & ~mask;
  298. tmp |= val & mask;
  299. rc = nvmem_device_write(chip->lpg_chan_nvmem,
  300. lpg->lpg_sdam_base + addr, 1, &tmp);
  301. if (rc < 0)
  302. dev_err(chip->dev, "write SDAM addr %d failed, rc=%d\n",
  303. lpg->lpg_sdam_base + addr, rc);
  304. unlock:
  305. mutex_unlock(&chip->bus_lock);
  306. return rc > 0 ? 0 : rc;
  307. }
  308. static int qpnp_lut_sdam_write(struct qpnp_lpg_lut *lut,
  309. u16 addr, u8 *val, size_t length)
  310. {
  311. struct qpnp_lpg_chip *chip = lut->chip;
  312. int rc;
  313. if (addr >= SDAM_LUT_COUNT_MAX)
  314. return -EINVAL;
  315. mutex_lock(&chip->bus_lock);
  316. rc = nvmem_device_write(chip->lut_nvmem,
  317. lut->reg_base + addr, length, val);
  318. if (rc < 0)
  319. dev_err(chip->dev, "write SDAM addr %d failed, rc=%d\n",
  320. lut->reg_base + addr, rc);
  321. mutex_unlock(&chip->bus_lock);
  322. return rc > 0 ? 0 : rc;
  323. }
  324. static struct qpnp_lpg_channel *pwm_dev_to_qpnp_lpg(struct pwm_chip *pwm_chip,
  325. struct pwm_device *pwm)
  326. {
  327. struct qpnp_lpg_chip *chip = container_of(pwm_chip,
  328. struct qpnp_lpg_chip, pwm_chip);
  329. u32 hw_idx = pwm->hwpwm;
  330. if (hw_idx >= chip->num_lpgs) {
  331. dev_err(chip->dev, "hw index %d out of range [0-%d]\n",
  332. hw_idx, chip->num_lpgs - 1);
  333. return NULL;
  334. }
  335. return &chip->lpgs[hw_idx];
  336. }
  337. static int __find_index_in_array(int member, const int array[], int length)
  338. {
  339. int i;
  340. for (i = 0; i < length; i++) {
  341. if (member == array[i])
  342. return i;
  343. }
  344. return -EINVAL;
  345. }
  346. static int qpnp_lpg_set_glitch_removal(struct qpnp_lpg_channel *lpg, bool en)
  347. {
  348. int rc;
  349. u8 mask, val;
  350. val = en ? LPG_PWM_EN_GLITCH_REMOVAL_MASK : 0;
  351. mask = LPG_PWM_EN_GLITCH_REMOVAL_MASK;
  352. rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_TYPE_CONFIG, mask, val);
  353. if (rc < 0)
  354. dev_err(lpg->chip->dev, "Write LPG_PWM_TYPE_CONFIG failed, rc=%d\n",
  355. rc);
  356. return rc;
  357. }
  358. static int qpnp_lpg_set_pwm_config(struct qpnp_lpg_channel *lpg)
  359. {
  360. int rc;
  361. u8 val, mask, shift;
  362. int pwm_size_idx, pwm_clk_idx, prediv_idx, clk_exp_idx;
  363. if (lpg->subtype == SUBTYPE_HI_RES_PWM) {
  364. pwm_size_idx = __find_index_in_array(lpg->pwm_config.pwm_size,
  365. pwm_hi_res_size, ARRAY_SIZE(pwm_hi_res_size));
  366. pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
  367. clk_freq_hz_hi_res, ARRAY_SIZE(clk_freq_hz_hi_res));
  368. } else {
  369. pwm_size_idx = __find_index_in_array(lpg->pwm_config.pwm_size,
  370. pwm_size, ARRAY_SIZE(pwm_size));
  371. pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
  372. clk_freq_hz, ARRAY_SIZE(clk_freq_hz));
  373. }
  374. prediv_idx = __find_index_in_array(lpg->pwm_config.prediv,
  375. clk_prediv, ARRAY_SIZE(clk_prediv));
  376. clk_exp_idx = __find_index_in_array(lpg->pwm_config.clk_exp,
  377. pwm_exponent, ARRAY_SIZE(pwm_exponent));
  378. if (pwm_size_idx < 0 || pwm_clk_idx < 0
  379. || prediv_idx < 0 || clk_exp_idx < 0)
  380. return -EINVAL;
  381. /* pwm_clk_idx is 1 bit lower than the register value */
  382. pwm_clk_idx += 1;
  383. if (lpg->subtype == SUBTYPE_PWM) {
  384. shift = LPG_PWM_SIZE_PWM_SHIFT;
  385. mask = LPG_PWM_SIZE_PWM_MASK | LPG_PWM_CLK_FREQ_SEL_MASK;
  386. } else if (lpg->subtype == SUBTYPE_HI_RES_PWM) {
  387. shift = LPG_PWM_SIZE_PWM_HI_RES_SHIFT;
  388. mask = LPG_PWM_SIZE_PWM_HI_RES_MASK | LPG_PWM_HI_RES_CLK_FREQ_SEL_MASK;
  389. } else {
  390. shift = LPG_PWM_SIZE_LPG_SHIFT;
  391. mask = LPG_PWM_SIZE_LPG_MASK | LPG_PWM_CLK_FREQ_SEL_MASK;
  392. }
  393. val = pwm_size_idx << shift | pwm_clk_idx;
  394. rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_SIZE_CLK, mask, val);
  395. if (rc < 0) {
  396. dev_err(lpg->chip->dev, "Write LPG_PWM_SIZE_CLK failed, rc=%d\n",
  397. rc);
  398. return rc;
  399. }
  400. val = prediv_idx << LPG_PWM_FREQ_PREDIV_SHIFT | clk_exp_idx;
  401. mask = LPG_PWM_FREQ_PREDIV_MASK | LPG_PWM_FREQ_EXPONENT_MASK;
  402. rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_FREQ_PREDIV_CLK, mask, val);
  403. if (rc < 0) {
  404. dev_err(lpg->chip->dev, "Write LPG_PWM_FREQ_PREDIV_CLK failed, rc=%d\n",
  405. rc);
  406. return rc;
  407. }
  408. if (lpg->src_sel == LUT_PATTERN)
  409. return 0;
  410. val = lpg->pwm_config.pwm_value >> 8;
  411. if (lpg->subtype == SUBTYPE_HI_RES_PWM)
  412. mask = LPG_PWM_HI_RES_VALUE_MSB_MASK;
  413. else
  414. mask = LPG_PWM_VALUE_MSB_MASK;
  415. rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_VALUE_MSB, mask, val);
  416. if (rc < 0) {
  417. dev_err(lpg->chip->dev, "Write LPG_PWM_VALUE_MSB failed, rc=%d\n",
  418. rc);
  419. return rc;
  420. }
  421. val = lpg->pwm_config.pwm_value & LPG_PWM_VALUE_LSB_MASK;
  422. rc = qpnp_lpg_write(lpg, REG_LPG_PWM_VALUE_LSB, val);
  423. if (rc < 0) {
  424. dev_err(lpg->chip->dev, "Write LPG_PWM_VALUE_LSB failed, rc=%d\n",
  425. rc);
  426. return rc;
  427. }
  428. val = LPG_PWM_VALUE_SYNC;
  429. rc = qpnp_lpg_write(lpg, REG_LPG_PWM_SYNC, val);
  430. if (rc < 0) {
  431. dev_err(lpg->chip->dev, "Write LPG_PWM_SYNC failed, rc=%d\n",
  432. rc);
  433. return rc;
  434. }
  435. return rc;
  436. }
  437. static int qpnp_lpg_set_pfm_config(struct qpnp_lpg_channel *lpg)
  438. {
  439. int rc;
  440. u8 val, mask;
  441. int pwm_clk_idx, clk_exp_idx;
  442. if (lpg->subtype == SUBTYPE_HI_RES_PWM)
  443. pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
  444. clk_freq_hz_hi_res, ARRAY_SIZE(clk_freq_hz_hi_res));
  445. else
  446. pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
  447. clk_freq_hz, ARRAY_SIZE(clk_freq_hz));
  448. clk_exp_idx = __find_index_in_array(lpg->pwm_config.clk_exp,
  449. pwm_exponent, ARRAY_SIZE(pwm_exponent));
  450. if (pwm_clk_idx < 0 || clk_exp_idx < 0)
  451. return -EINVAL;
  452. /* pwm_clk_idx is 1 bit lower than the register value */
  453. pwm_clk_idx += 1;
  454. val = pwm_clk_idx;
  455. if (lpg->subtype == SUBTYPE_HI_RES_PWM)
  456. mask = LPG_PWM_HI_RES_CLK_FREQ_SEL_MASK;
  457. else
  458. mask = LPG_PWM_CLK_FREQ_SEL_MASK;
  459. rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_SIZE_CLK, mask, val);
  460. if (rc < 0) {
  461. dev_err(lpg->chip->dev, "Write LPG_PWM_SIZE_CLK failed, rc=%d\n",
  462. rc);
  463. return rc;
  464. }
  465. val = clk_exp_idx;
  466. mask = LPG_PWM_FREQ_EXPONENT_MASK;
  467. rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_FREQ_PREDIV_CLK, mask, val);
  468. if (rc < 0) {
  469. dev_err(lpg->chip->dev, "Write LPG_PWM_FREQ_PREDIV_CLK failed, rc=%d\n",
  470. rc);
  471. return rc;
  472. }
  473. val = lpg->pwm_config.pwm_value;
  474. rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_VALUE_LSB,
  475. LPG_PWM_VALUE_LSB_MASK, val);
  476. if (rc < 0) {
  477. dev_err(lpg->chip->dev, "Write LPG_PWM_VALUE_LSB failed, rc=%d\n",
  478. rc);
  479. return rc;
  480. }
  481. val = LPG_PWM_VALUE_SYNC;
  482. rc = qpnp_lpg_write(lpg, REG_LPG_PWM_SYNC, val);
  483. if (rc < 0) {
  484. dev_err(lpg->chip->dev, "Write LPG_PWM_SYNC failed, rc=%d\n",
  485. rc);
  486. return rc;
  487. }
  488. return rc;
  489. }
  490. static int qpnp_lpg_set_sdam_lut_pattern(struct qpnp_lpg_channel *lpg,
  491. unsigned int *pattern, unsigned int length)
  492. {
  493. struct qpnp_lpg_lut *lut = lpg->chip->lut;
  494. int i, rc = 0;
  495. u8 val[SDAM_LUT_COUNT_MAX + 1], addr;
  496. if (length > lpg->max_pattern_length) {
  497. dev_err(lpg->chip->dev, "new pattern length (%d) larger than predefined (%d)\n",
  498. length, lpg->max_pattern_length);
  499. return -EINVAL;
  500. }
  501. /* Program LUT pattern */
  502. mutex_lock(&lut->lock);
  503. addr = lpg->ramp_config.lo_idx;
  504. for (i = 0; i < length; i++)
  505. val[i] = pattern[i] * 255 / 100;
  506. rc = qpnp_lut_sdam_write(lut, addr, val, length);
  507. if (rc < 0) {
  508. dev_err(lpg->chip->dev, "Write pattern in SDAM failed, rc=%d\n",
  509. rc);
  510. goto unlock;
  511. }
  512. lpg->ramp_config.pattern_length = length;
  513. unlock:
  514. mutex_unlock(&lut->lock);
  515. return rc;
  516. }
  517. #define SDAM_START_BASE 0x40
  518. static u8 qpnp_lpg_get_sdam_lut_idx(struct qpnp_lpg_channel *lpg, u8 idx)
  519. {
  520. struct qpnp_lpg_chip *chip = lpg->chip;
  521. u8 val = idx;
  522. if (chip->lut->nvmem_count == PPG_NVMEMS_2)
  523. val += (chip->lut->reg_base - SDAM_START_BASE);
  524. return val;
  525. }
  526. static int qpnp_lpg_set_sdam_ramp_config(struct qpnp_lpg_channel *lpg)
  527. {
  528. struct lpg_ramp_config *ramp = &lpg->ramp_config;
  529. u8 addr, mask, val;
  530. int rc = 0;
  531. /* clear PBS scatchpad register */
  532. val = 0;
  533. rc = qpnp_lpg_sdam_write(lpg,
  534. SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET, val);
  535. if (rc < 0) {
  536. dev_err(lpg->chip->dev, "Write SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET failed, rc=%d\n",
  537. rc);
  538. return rc;
  539. }
  540. /* Set ramp step duration, in ticks */
  541. val = (ramp->step_ms * 1000 / lpg->chip->lut->ramp_step_tick_us) & 0xff;
  542. if (val > 0)
  543. val--;
  544. addr = SDAM_REG_RAMP_STEP_DURATION;
  545. rc = qpnp_lpg_chan_nvmem_write(lpg->chip, addr, val);
  546. if (rc < 0) {
  547. dev_err(lpg->chip->dev, "Write SDAM_REG_RAMP_STEP_DURATION failed, rc=%d\n",
  548. rc);
  549. return rc;
  550. }
  551. /* Set hi_idx and lo_idx */
  552. val = qpnp_lpg_get_sdam_lut_idx(lpg, ramp->hi_idx);
  553. rc = qpnp_lpg_sdam_write(lpg, SDAM_END_INDEX_OFFSET, val);
  554. if (rc < 0) {
  555. dev_err(lpg->chip->dev, "Write SDAM_REG_END_INDEX failed, rc=%d\n",
  556. rc);
  557. return rc;
  558. }
  559. val = qpnp_lpg_get_sdam_lut_idx(lpg, ramp->lo_idx);
  560. rc = qpnp_lpg_sdam_write(lpg, SDAM_START_INDEX_OFFSET, val);
  561. if (rc < 0) {
  562. dev_err(lpg->chip->dev, "Write SDAM_REG_START_INDEX failed, rc=%d\n",
  563. rc);
  564. return rc;
  565. }
  566. /* Set LPG_PATTERN_CONFIG */
  567. addr = SDAM_PATTERN_CONFIG_OFFSET;
  568. mask = SDAM_PATTERN_LOOP_ENABLE;
  569. val = 0;
  570. if (ramp->pattern_repeat)
  571. val |= SDAM_PATTERN_LOOP_ENABLE;
  572. if (ramp->pause_hi_count) {
  573. val |= SDAM_PATTERN_EN_PAUSE_START;
  574. mask |= SDAM_PATTERN_EN_PAUSE_START;
  575. }
  576. if (ramp->pause_lo_count) {
  577. val |= SDAM_PATTERN_EN_PAUSE_END;
  578. mask |= SDAM_PATTERN_EN_PAUSE_END;
  579. }
  580. rc = qpnp_lpg_sdam_masked_write(lpg, addr, mask, val);
  581. if (rc < 0) {
  582. dev_err(lpg->chip->dev, "Write SDAM_REG_PATTERN_CONFIG failed, rc=%d\n",
  583. rc);
  584. return rc;
  585. }
  586. /* Set PAUSE HI and LO */
  587. rc = qpnp_lpg_sdam_write(lpg, SDAM_PAUSE_START_MULTIPLIER_OFFSET,
  588. ramp->pause_hi_count);
  589. if (rc < 0) {
  590. dev_err(lpg->chip->dev, "Write SDAM_REG_PAUSE_START_MULTIPLIER failed, rc=%d\n",
  591. rc);
  592. return rc;
  593. }
  594. rc = qpnp_lpg_sdam_write(lpg, SDAM_PAUSE_END_MULTIPLIER_OFFSET,
  595. ramp->pause_lo_count);
  596. if (rc < 0) {
  597. dev_err(lpg->chip->dev, "Write SDAM_REG_PAUSE_END_MULTIPLIER failed, rc=%d\n",
  598. rc);
  599. return rc;
  600. }
  601. return rc;
  602. }
  603. static int qpnp_lpg_set_lut_pattern(struct qpnp_lpg_channel *lpg,
  604. unsigned int *pattern, unsigned int length)
  605. {
  606. struct qpnp_lpg_lut *lut = lpg->chip->lut;
  607. u16 full_duty_value, pwm_values[SDAM_LUT_COUNT_MAX + 1] = {0};
  608. int i, rc = 0;
  609. u8 lsb, msb, addr;
  610. if (lpg->chip->use_sdam)
  611. return qpnp_lpg_set_sdam_lut_pattern(lpg, pattern, length);
  612. if (length > lpg->max_pattern_length) {
  613. dev_err(lpg->chip->dev, "new pattern length (%d) larger than predefined (%d)\n",
  614. length, lpg->max_pattern_length);
  615. return -EINVAL;
  616. }
  617. /* Program LUT pattern */
  618. mutex_lock(&lut->lock);
  619. addr = REG_LPG_LUT_1_LSB + lpg->ramp_config.lo_idx * 2;
  620. for (i = 0; i < length; i++) {
  621. full_duty_value = 1 << lpg->pwm_config.pwm_size;
  622. pwm_values[i] = pattern[i] * full_duty_value / 100;
  623. if (unlikely(pwm_values[i] > full_duty_value)) {
  624. dev_err(lpg->chip->dev, "PWM value %d exceed the max %d\n",
  625. pwm_values[i], full_duty_value);
  626. rc = -EINVAL;
  627. goto unlock;
  628. }
  629. if (pwm_values[i] == full_duty_value)
  630. pwm_values[i] = full_duty_value - 1;
  631. lsb = pwm_values[i] & 0xff;
  632. msb = pwm_values[i] >> 8;
  633. rc = qpnp_lut_write(lut, addr++, lsb);
  634. if (rc < 0) {
  635. dev_err(lpg->chip->dev, "Write NO.%d LUT pattern LSB (%d) failed, rc=%d\n",
  636. i, lsb, rc);
  637. goto unlock;
  638. }
  639. rc = qpnp_lut_masked_write(lut, addr++,
  640. LPG_LUT_VALUE_MSB_MASK, msb);
  641. if (rc < 0) {
  642. dev_err(lpg->chip->dev, "Write NO.%d LUT pattern MSB (%d) failed, rc=%d\n",
  643. i, msb, rc);
  644. goto unlock;
  645. }
  646. }
  647. lpg->ramp_config.pattern_length = length;
  648. unlock:
  649. mutex_unlock(&lut->lock);
  650. return rc;
  651. }
  652. static int qpnp_lpg_set_ramp_config(struct qpnp_lpg_channel *lpg)
  653. {
  654. struct lpg_ramp_config *ramp = &lpg->ramp_config;
  655. u8 lsb, msb, addr, mask, val;
  656. int rc = 0;
  657. if (lpg->chip->use_sdam)
  658. return qpnp_lpg_set_sdam_ramp_config(lpg);
  659. /* Set ramp step duration */
  660. lsb = ramp->step_ms & 0xff;
  661. msb = ramp->step_ms >> 8;
  662. addr = REG_LPG_RAMP_STEP_DURATION_LSB;
  663. rc = qpnp_lpg_write(lpg, addr, lsb);
  664. if (rc < 0) {
  665. dev_err(lpg->chip->dev, "Write RAMP_STEP_DURATION_LSB failed, rc=%d\n",
  666. rc);
  667. return rc;
  668. }
  669. rc = qpnp_lpg_write(lpg, addr + 1, msb);
  670. if (rc < 0) {
  671. dev_err(lpg->chip->dev, "Write RAMP_STEP_DURATION_MSB failed, rc=%d\n",
  672. rc);
  673. return rc;
  674. }
  675. /* Set hi_idx and lo_idx */
  676. rc = qpnp_lpg_masked_write(lpg, REG_LPG_HI_INDEX,
  677. LPG_HI_LO_IDX_MASK, ramp->hi_idx);
  678. if (rc < 0) {
  679. dev_err(lpg->chip->dev, "Write LPG_HI_IDX failed, rc=%d\n",
  680. rc);
  681. return rc;
  682. }
  683. rc = qpnp_lpg_masked_write(lpg, REG_LPG_LO_INDEX,
  684. LPG_HI_LO_IDX_MASK, ramp->lo_idx);
  685. if (rc < 0) {
  686. dev_err(lpg->chip->dev, "Write LPG_LO_IDX failed, rc=%d\n",
  687. rc);
  688. return rc;
  689. }
  690. /* Set pause_hi/lo_count */
  691. rc = qpnp_lpg_write(lpg, REG_LPG_PAUSE_HI_MULTIPLIER,
  692. ramp->pause_hi_count);
  693. if (rc < 0) {
  694. dev_err(lpg->chip->dev, "Write LPG_PAUSE_HI_MULTIPLIER failed, rc=%d\n",
  695. rc);
  696. return rc;
  697. }
  698. rc = qpnp_lpg_write(lpg, REG_LPG_PAUSE_LO_MULTIPLIER,
  699. ramp->pause_lo_count);
  700. if (rc < 0) {
  701. dev_err(lpg->chip->dev, "Write LPG_PAUSE_LO_MULTIPLIER failed, rc=%d\n",
  702. rc);
  703. return rc;
  704. }
  705. /* Set LPG_PATTERN_CONFIG */
  706. addr = REG_LPG_PATTERN_CONFIG;
  707. mask = LPG_PATTERN_EN_PAUSE_LO | LPG_PATTERN_EN_PAUSE_HI
  708. | LPG_PATTERN_RAMP_TOGGLE | LPG_PATTERN_REPEAT
  709. | LPG_PATTERN_RAMP_LO_TO_HI;
  710. val = 0;
  711. if (ramp->pause_lo_count != 0)
  712. val |= LPG_PATTERN_EN_PAUSE_LO;
  713. if (ramp->pause_hi_count != 0)
  714. val |= LPG_PATTERN_EN_PAUSE_HI;
  715. if (ramp->ramp_dir_low_to_hi)
  716. val |= LPG_PATTERN_RAMP_LO_TO_HI;
  717. if (ramp->pattern_repeat)
  718. val |= LPG_PATTERN_REPEAT;
  719. if (ramp->toggle)
  720. val |= LPG_PATTERN_RAMP_TOGGLE;
  721. rc = qpnp_lpg_masked_write(lpg, addr, mask, val);
  722. if (rc < 0) {
  723. dev_err(lpg->chip->dev, "Write LPG_PATTERN_CONFIG failed, rc=%d\n",
  724. rc);
  725. return rc;
  726. }
  727. return rc;
  728. }
  729. static int __qpnp_lpg_calc_pwm_period(u64 period_ns,
  730. struct lpg_pwm_config *pwm_config)
  731. {
  732. struct qpnp_lpg_channel *lpg = container_of(pwm_config,
  733. struct qpnp_lpg_channel, pwm_config);
  734. struct lpg_pwm_config configs[NUM_PWM_HI_RES_SIZE];
  735. int i, j, m, n;
  736. u64 tmp1, tmp2;
  737. u64 clk_period_ns = 0, pwm_clk_period_ns;
  738. u64 clk_delta_ns = U64_MAX, min_clk_delta_ns = U64_MAX;
  739. u64 pwm_period_delta = U64_MAX, min_pwm_period_delta = U64_MAX;
  740. int pwm_size_step, clk_len, pwm_size_len;
  741. const int *pwm_size_arr, *clk_freq_hz_arr;
  742. /*
  743. * (2^pwm_size) * (2^pwm_exp) * prediv * NSEC_PER_SEC
  744. * pwm_period = ---------------------------------------------------
  745. * clk_freq_hz
  746. *
  747. * Searching the closest settings for the requested PWM period.
  748. */
  749. if (lpg->subtype == SUBTYPE_HI_RES_PWM) {
  750. pwm_size_arr = pwm_hi_res_size;
  751. pwm_size_len = NUM_PWM_HI_RES_SIZE;
  752. clk_freq_hz_arr = clk_freq_hz_hi_res;
  753. clk_len = NUM_PWM_HI_RES_CLK;
  754. } else {
  755. pwm_size_arr = pwm_size;
  756. pwm_size_len = NUM_PWM_SIZE;
  757. clk_freq_hz_arr = clk_freq_hz;
  758. clk_len = NUM_PWM_CLK;
  759. }
  760. if (lpg->chip->use_sdam) {
  761. /* SDAM pattern control can only use 9 bit resolution */
  762. n = 1;
  763. pwm_size_len = 2;
  764. }
  765. else
  766. n = 0;
  767. for (; n < pwm_size_len; n++) {
  768. pwm_clk_period_ns = period_ns >> pwm_size_arr[n];
  769. for (i = clk_len - 1; i >= 0; i--) {
  770. for (j = 0; j < clk_len; j++) {
  771. for (m = 0; m < ARRAY_SIZE(pwm_exponent); m++) {
  772. tmp1 = 1 << pwm_exponent[m];
  773. tmp1 *= clk_prediv[j];
  774. tmp2 = NSEC_PER_SEC;
  775. do_div(tmp2, clk_freq_hz_arr[i]);
  776. clk_period_ns = tmp1 * tmp2;
  777. clk_delta_ns = abs(pwm_clk_period_ns
  778. - clk_period_ns);
  779. /*
  780. * Find the closest setting for
  781. * PWM frequency predivide value
  782. */
  783. if (clk_delta_ns < min_clk_delta_ns) {
  784. min_clk_delta_ns
  785. = clk_delta_ns;
  786. configs[n].pwm_clk
  787. = clk_freq_hz_arr[i];
  788. configs[n].prediv
  789. = clk_prediv[j];
  790. configs[n].clk_exp
  791. = pwm_exponent[m];
  792. configs[n].pwm_size
  793. = pwm_size_arr[n];
  794. configs[n].best_period_ns
  795. = clk_period_ns;
  796. }
  797. }
  798. }
  799. }
  800. configs[n].best_period_ns *= 1 << pwm_size_arr[n];
  801. /* Find the closest setting for PWM period */
  802. pwm_period_delta = min_clk_delta_ns << pwm_size_arr[n];
  803. if (pwm_period_delta < min_pwm_period_delta) {
  804. min_pwm_period_delta = pwm_period_delta;
  805. memcpy(pwm_config, &configs[n],
  806. sizeof(struct lpg_pwm_config));
  807. }
  808. }
  809. /* Larger PWM size can achieve better resolution for PWM duty */
  810. for (n = pwm_size_len - 1; n > 0; n--) {
  811. if (pwm_config->pwm_size >= pwm_size_arr[n])
  812. break;
  813. pwm_size_step = pwm_size_arr[n] - pwm_config->pwm_size;
  814. if (pwm_config->clk_exp >= pwm_size_step) {
  815. pwm_config->pwm_size = pwm_size_arr[n];
  816. pwm_config->clk_exp -= pwm_size_step;
  817. }
  818. }
  819. pr_debug("PWM setting for period_ns %llu: pwm_clk = %dHZ, prediv = %d, exponent = %d, pwm_size = %d\n",
  820. period_ns, pwm_config->pwm_clk, pwm_config->prediv,
  821. pwm_config->clk_exp, pwm_config->pwm_size);
  822. pr_debug("Actual period: %lluns\n", pwm_config->best_period_ns);
  823. return 0;
  824. }
  825. static void __qpnp_lpg_calc_pwm_duty(u64 period_ns, u64 duty_ns,
  826. struct lpg_pwm_config *pwm_config)
  827. {
  828. u16 pwm_value, max_pwm_value;
  829. u64 tmp;
  830. tmp = (u64)duty_ns << pwm_config->pwm_size;
  831. pwm_value = (u16)div64_u64(tmp, period_ns);
  832. max_pwm_value = (1 << pwm_config->pwm_size) - 1;
  833. if (pwm_value > max_pwm_value)
  834. pwm_value = max_pwm_value;
  835. pwm_config->pwm_value = pwm_value;
  836. }
  837. static int __qpnp_lpg_calc_pfm_period(u64 period_ns,
  838. struct lpg_pwm_config *pwm_config)
  839. {
  840. struct qpnp_lpg_channel *lpg = container_of(pwm_config,
  841. struct qpnp_lpg_channel, pwm_config);
  842. int clk, exp, lsb, clk_len;
  843. int best_clk = 0, best_exp = 0, best_lsb = -EINVAL;
  844. u64 lsb_tmp, period_tmp, curr_p_err, last_p_err = 0;
  845. u64 min_p_err = U64_MAX;
  846. const int *clk_freq_hz_arr, *clk_period_ns_arr;
  847. /*
  848. * 2 * (pwm_value_lsb + 1) * (2^pwm_exp) * NSEC_PER_SEC
  849. * pwm_period = ---------------------------------------------------
  850. * clk_freq_hz
  851. *
  852. * For each (clk, exp) solve above equation for pwm_value_lsb, and then
  853. * use this pwm_lsb to calculate pwm_period and compare with desired
  854. * period. Store the triplet values that yield the closest value to
  855. * desired period.
  856. */
  857. if (lpg->subtype == SUBTYPE_HI_RES_PWM) {
  858. clk_freq_hz_arr = clk_freq_hz_hi_res;
  859. clk_period_ns_arr = clk_period_ns_hi_res;
  860. clk_len = NUM_PWM_HI_RES_CLK;
  861. } else {
  862. clk_freq_hz_arr = clk_freq_hz;
  863. clk_period_ns_arr = clk_period_ns;
  864. clk_len = NUM_PWM_CLK;
  865. }
  866. for (clk = 0; clk < clk_len; clk++) {
  867. last_p_err = U64_MAX;
  868. for (exp = 0; exp < NUM_PWM_EXP; exp++) {
  869. lsb_tmp = div_u64(period_ns, clk_period_ns_arr[clk]);
  870. lsb_tmp >>= (exp + 1);
  871. lsb = lsb_tmp - 1;
  872. if (lsb >= 0 && lsb <= U8_MAX) {
  873. period_tmp = (lsb + 1);
  874. period_tmp <<= (exp + 1);
  875. period_tmp *= clk_period_ns_arr[clk];
  876. curr_p_err = abs(period_ns - period_tmp);
  877. if (curr_p_err < min_p_err) {
  878. min_p_err = curr_p_err;
  879. /* Closest settings found! Save them. */
  880. best_clk = clk;
  881. best_exp = exp;
  882. best_lsb = lsb;
  883. /*
  884. * No need to set pwm_size or prediv in
  885. * `struct pwm_config` as they are
  886. * no-ops in PFM mode.
  887. */
  888. pwm_config->best_period_ns = period_tmp;
  889. }
  890. if (curr_p_err > last_p_err)
  891. /* No need to iterate further */
  892. break;
  893. last_p_err = curr_p_err;
  894. }
  895. }
  896. }
  897. if (best_lsb < 0) {
  898. pr_err("Cannot generate %llu ns\n", period_ns);
  899. return -EINVAL;
  900. }
  901. pwm_config->pwm_clk = clk_freq_hz_arr[best_clk];
  902. pwm_config->clk_exp = pwm_exponent[best_exp];
  903. pwm_config->pwm_value = best_lsb;
  904. pr_debug("PFM setting for period_ns %llu: pwm_clk = %d Hz, exponent = %d, pwm_val_lsb = %d\n",
  905. period_ns, pwm_config->pwm_clk,
  906. pwm_config->clk_exp, pwm_config->pwm_value);
  907. pr_debug("Actual PFM period: %llu ns\n", pwm_config->best_period_ns);
  908. return 0;
  909. }
  910. static int qpnp_lpg_config(struct qpnp_lpg_channel *lpg,
  911. u64 duty_ns, u64 period_ns)
  912. {
  913. int rc;
  914. if (duty_ns > period_ns) {
  915. dev_err(lpg->chip->dev, "Duty %lluns is larger than period %lluns\n",
  916. duty_ns, period_ns);
  917. return -EINVAL;
  918. }
  919. if (period_ns != lpg->current_period_ns) {
  920. if (lpg->enable_pfm) {
  921. rc = __qpnp_lpg_calc_pfm_period(period_ns,
  922. &lpg->pwm_config);
  923. if (rc)
  924. return rc;
  925. } else {
  926. rc = __qpnp_lpg_calc_pwm_period(period_ns,
  927. &lpg->pwm_config);
  928. if (rc)
  929. return rc;
  930. /* program LUT if PWM period is changed */
  931. if (lpg->src_sel == LUT_PATTERN) {
  932. rc = qpnp_lpg_set_lut_pattern(lpg,
  933. lpg->ramp_config.pattern,
  934. lpg->ramp_config.pattern_length);
  935. if (rc < 0) {
  936. dev_err(lpg->chip->dev, "set LUT pattern failed for LPG%d, rc=%d\n",
  937. lpg->lpg_idx, rc);
  938. return rc;
  939. }
  940. lpg->lut_written = true;
  941. }
  942. }
  943. }
  944. /* Don't calculate duty cycle for PFM as it is fixed at 50% */
  945. if ((period_ns != lpg->current_period_ns ||
  946. duty_ns != lpg->current_duty_ns) && !lpg->enable_pfm)
  947. __qpnp_lpg_calc_pwm_duty(period_ns, duty_ns, &lpg->pwm_config);
  948. if (lpg->enable_pfm)
  949. rc = qpnp_lpg_set_pfm_config(lpg);
  950. else
  951. rc = qpnp_lpg_set_pwm_config(lpg);
  952. if (rc < 0) {
  953. dev_err(lpg->chip->dev, "Config %s failed for channel %d, rc=%d\n",
  954. lpg->enable_pfm ? "PFM" : "PWM", lpg->lpg_idx, rc);
  955. return rc;
  956. }
  957. lpg->current_period_ns = period_ns;
  958. lpg->current_duty_ns = duty_ns;
  959. return rc;
  960. }
  961. static int qpnp_lpg_pwm_config(struct pwm_chip *pwm_chip,
  962. struct pwm_device *pwm, u64 duty_ns, u64 period_ns)
  963. {
  964. struct qpnp_lpg_channel *lpg;
  965. lpg = pwm_dev_to_qpnp_lpg(pwm_chip, pwm);
  966. if (lpg == NULL) {
  967. dev_err(pwm_chip->dev, "lpg not found\n");
  968. return -ENODEV;
  969. }
  970. return qpnp_lpg_config(lpg, duty_ns, period_ns);
  971. }
  972. #define SDAM_PBS_TRIG_SET 0xe5
  973. #define SDAM_PBS_TRIG_CLR 0xe6
  974. static int qpnp_lpg_clear_pbs_trigger(struct qpnp_lpg_chip *chip)
  975. {
  976. int rc;
  977. rc = qpnp_lpg_chan_nvmem_write(chip,
  978. SDAM_REG_PBS_SEQ_EN, 0);
  979. if (rc < 0) {
  980. dev_err(chip->dev, "Write SDAM_REG_PBS_SEQ_EN failed, rc=%d\n",
  981. rc);
  982. return rc;
  983. }
  984. if (chip->lut->nvmem_count == PPG_NVMEMS_2) {
  985. rc = qpnp_lpg_chan_nvmem_write(chip, SDAM_PBS_TRIG_CLR,
  986. PBS_SW_TRG_BIT);
  987. if (rc < 0) {
  988. dev_err(chip->dev, "Failed to fire PBS seq, rc=%d\n",
  989. rc);
  990. return rc;
  991. }
  992. }
  993. return 0;
  994. }
  995. static int qpnp_lpg_set_pbs_trigger(struct qpnp_lpg_chip *chip)
  996. {
  997. int rc;
  998. rc = qpnp_lpg_chan_nvmem_write(chip,
  999. SDAM_REG_PBS_SEQ_EN, PBS_SW_TRG_BIT);
  1000. if (rc < 0) {
  1001. dev_err(chip->dev, "Write SDAM_REG_PBS_SEQ_EN failed, rc=%d\n",
  1002. rc);
  1003. return rc;
  1004. }
  1005. if (chip->lut->nvmem_count == PPG_NVMEMS_1) {
  1006. if (!chip->pbs_dev_node) {
  1007. dev_err(chip->dev, "PBS device unavailable\n");
  1008. return -ENODEV;
  1009. }
  1010. rc = qpnp_pbs_trigger_event(chip->pbs_dev_node,
  1011. PBS_SW_TRG_BIT);
  1012. } else {
  1013. rc = qpnp_lpg_chan_nvmem_write(chip, SDAM_PBS_TRIG_SET,
  1014. PBS_SW_TRG_BIT);
  1015. }
  1016. if (rc < 0)
  1017. dev_err(chip->dev, "Failed to trigger PBS, rc=%d\n", rc);
  1018. return rc;
  1019. }
  1020. static int qpnp_lpg_pbs_trigger_enable(struct qpnp_lpg_channel *lpg, bool en)
  1021. {
  1022. struct qpnp_lpg_chip *chip = lpg->chip;
  1023. int rc = 0;
  1024. if (en) {
  1025. if (chip->pbs_en_bitmap == 0) {
  1026. rc = qpnp_lpg_set_pbs_trigger(chip);
  1027. if (rc < 0)
  1028. return rc;
  1029. }
  1030. set_bit(lpg->lpg_idx, &chip->pbs_en_bitmap);
  1031. } else {
  1032. clear_bit(lpg->lpg_idx, &chip->pbs_en_bitmap);
  1033. if (chip->pbs_en_bitmap == 0) {
  1034. rc = qpnp_lpg_clear_pbs_trigger(chip);
  1035. if (rc < 0)
  1036. return rc;
  1037. }
  1038. }
  1039. return rc;
  1040. }
  1041. static int qpnp_lpg_pwm_src_enable(struct qpnp_lpg_channel *lpg, bool en)
  1042. {
  1043. struct qpnp_lpg_chip *chip = lpg->chip;
  1044. struct qpnp_lpg_lut *lut = chip->lut;
  1045. struct pwm_device *pwm;
  1046. u8 mask, val;
  1047. int i, lpg_idx, rc;
  1048. mask = LPG_PWM_SRC_SELECT_MASK | LPG_EN_LPG_OUT_BIT |
  1049. LPG_EN_RAMP_GEN_MASK;
  1050. val = lpg->src_sel << LPG_PWM_SRC_SELECT_SHIFT;
  1051. if (lpg->src_sel == LUT_PATTERN && !chip->use_sdam)
  1052. val |= 1 << LPG_EN_RAMP_GEN_SHIFT;
  1053. if (en)
  1054. val |= 1 << LPG_EN_LPG_OUT_SHIFT;
  1055. rc = qpnp_lpg_masked_write(lpg, REG_LPG_ENABLE_CONTROL, mask, val);
  1056. if (rc < 0) {
  1057. dev_err(chip->dev, "Write LPG_ENABLE_CONTROL failed, rc=%d\n",
  1058. rc);
  1059. return rc;
  1060. }
  1061. if (chip->use_sdam) {
  1062. if (lpg->src_sel == LUT_PATTERN && en) {
  1063. val = SDAM_LUT_EN_BIT;
  1064. en = true;
  1065. } else {
  1066. val = 0;
  1067. en = false;
  1068. }
  1069. rc = qpnp_lpg_sdam_write(lpg, SDAM_LUT_EN_OFFSET, val);
  1070. if (rc < 0) {
  1071. dev_err(chip->dev, "Write SDAM_REG_LUT_EN failed, rc=%d\n",
  1072. rc);
  1073. return rc;
  1074. }
  1075. qpnp_lpg_pbs_trigger_enable(lpg, en);
  1076. return rc;
  1077. }
  1078. if (lpg->src_sel == LUT_PATTERN && en) {
  1079. val = 1 << lpg->lpg_idx;
  1080. for (i = 0; i < chip->num_lpgs; i++) {
  1081. if (chip->lpg_group == NULL)
  1082. break;
  1083. if (chip->lpg_group[i] == 0)
  1084. break;
  1085. lpg_idx = chip->lpg_group[i] - 1;
  1086. pwm = &chip->pwm_chip.pwms[lpg_idx];
  1087. if ((lpg->output_type == PWM_OUTPUT_MODULATED)
  1088. && pwm_is_enabled(pwm)) {
  1089. rc = qpnp_lpg_masked_write(&chip->lpgs[lpg_idx],
  1090. REG_LPG_ENABLE_CONTROL,
  1091. LPG_EN_LPG_OUT_BIT, 0);
  1092. if (rc < 0)
  1093. break;
  1094. rc = qpnp_lpg_masked_write(&chip->lpgs[lpg_idx],
  1095. REG_LPG_ENABLE_CONTROL,
  1096. LPG_EN_LPG_OUT_BIT,
  1097. LPG_EN_LPG_OUT_BIT);
  1098. if (rc < 0)
  1099. break;
  1100. val |= 1 << lpg_idx;
  1101. }
  1102. }
  1103. mutex_lock(&lut->lock);
  1104. rc = qpnp_lut_write(lut, REG_LPG_LUT_RAMP_CONTROL, val);
  1105. if (rc < 0)
  1106. dev_err(chip->dev, "Write LPG_LUT_RAMP_CONTROL failed, rc=%d\n",
  1107. rc);
  1108. mutex_unlock(&lut->lock);
  1109. }
  1110. return rc;
  1111. }
  1112. int qpnp_lpg_pwm_set_output_type(struct pwm_device *pwm,
  1113. enum pwm_output_type output_type)
  1114. {
  1115. struct qpnp_lpg_channel *lpg;
  1116. enum lpg_src src_sel;
  1117. int rc;
  1118. bool is_enabled;
  1119. if (!pwm) {
  1120. pr_err("pwm cannot be NULL\n");
  1121. return -ENODEV;
  1122. }
  1123. lpg = pwm_dev_to_qpnp_lpg(pwm->chip, pwm);
  1124. if (lpg == NULL) {
  1125. dev_err(pwm->chip->dev, "lpg not found\n");
  1126. return -ENODEV;
  1127. }
  1128. if (lpg->chip->lut == NULL) {
  1129. pr_debug("lpg%d only support PWM mode\n", lpg->lpg_idx);
  1130. return 0;
  1131. }
  1132. if (output_type == lpg->output_type)
  1133. return 0;
  1134. src_sel = (output_type == PWM_OUTPUT_MODULATED) ?
  1135. LUT_PATTERN : PWM_VALUE;
  1136. if (src_sel == lpg->src_sel)
  1137. return 0;
  1138. is_enabled = pwm_is_enabled(pwm);
  1139. if (is_enabled) {
  1140. /*
  1141. * Disable the channel first then enable it later to make
  1142. * sure the output type is changed successfully. This is
  1143. * especially useful in SDAM use case to stop the PBS
  1144. * sequence when changing the PWM output type from
  1145. * MODULATED to FIXED.
  1146. */
  1147. rc = qpnp_lpg_pwm_src_enable(lpg, false);
  1148. if (rc < 0) {
  1149. dev_err(pwm->chip->dev, "Enable PWM output failed for channel %d, rc=%d\n",
  1150. lpg->lpg_idx, rc);
  1151. return rc;
  1152. }
  1153. }
  1154. if (src_sel == LUT_PATTERN) {
  1155. /* program LUT if it's never been programmed */
  1156. if (!lpg->lut_written) {
  1157. rc = qpnp_lpg_set_lut_pattern(lpg,
  1158. lpg->ramp_config.pattern,
  1159. lpg->ramp_config.pattern_length);
  1160. if (rc < 0) {
  1161. dev_err(lpg->chip->dev, "set LUT pattern failed for LPG%d, rc=%d\n",
  1162. lpg->lpg_idx, rc);
  1163. return rc;
  1164. }
  1165. lpg->lut_written = true;
  1166. }
  1167. rc = qpnp_lpg_set_ramp_config(lpg);
  1168. if (rc < 0) {
  1169. dev_err(pwm->chip->dev, "Config LPG%d ramping failed, rc=%d\n",
  1170. lpg->lpg_idx, rc);
  1171. return rc;
  1172. }
  1173. }
  1174. lpg->src_sel = src_sel;
  1175. if (is_enabled) {
  1176. rc = qpnp_lpg_set_pwm_config(lpg);
  1177. if (rc < 0) {
  1178. dev_err(pwm->chip->dev, "Config PWM failed for channel %d, rc=%d\n",
  1179. lpg->lpg_idx, rc);
  1180. return rc;
  1181. }
  1182. rc = qpnp_lpg_pwm_src_enable(lpg, true);
  1183. if (rc < 0) {
  1184. dev_err(pwm->chip->dev, "Enable PWM output failed for channel %d, rc=%d\n",
  1185. lpg->lpg_idx, rc);
  1186. return rc;
  1187. }
  1188. }
  1189. lpg->output_type = output_type;
  1190. return 0;
  1191. }
  1192. EXPORT_SYMBOL(qpnp_lpg_pwm_set_output_type);
  1193. int qpnp_lpg_pwm_get_output_types_supported(struct pwm_device *pwm)
  1194. {
  1195. enum pwm_output_type type = PWM_OUTPUT_FIXED;
  1196. struct qpnp_lpg_channel *lpg;
  1197. if (!pwm) {
  1198. pr_err("pwm cannot be NULL\n");
  1199. return -ENODEV;
  1200. }
  1201. lpg = pwm_dev_to_qpnp_lpg(pwm->chip, pwm);
  1202. if (lpg == NULL) {
  1203. dev_err(pwm->chip->dev, "lpg not found\n");
  1204. return -ENODEV;
  1205. }
  1206. if (lpg->chip->lut != NULL)
  1207. type |= PWM_OUTPUT_MODULATED;
  1208. return type;
  1209. }
  1210. EXPORT_SYMBOL(qpnp_lpg_pwm_get_output_types_supported);
  1211. static int qpnp_lpg_pwm_enable(struct pwm_chip *pwm_chip,
  1212. struct pwm_device *pwm)
  1213. {
  1214. struct qpnp_lpg_channel *lpg;
  1215. int rc = 0;
  1216. lpg = pwm_dev_to_qpnp_lpg(pwm_chip, pwm);
  1217. if (lpg == NULL) {
  1218. dev_err(pwm_chip->dev, "lpg not found\n");
  1219. return -ENODEV;
  1220. }
  1221. /*
  1222. * Update PWM_VALUE_SYNC to make sure PWM_VALUE
  1223. * will be updated everytime before enabling.
  1224. */
  1225. if (lpg->src_sel == PWM_VALUE) {
  1226. rc = qpnp_lpg_write(lpg, REG_LPG_PWM_SYNC, LPG_PWM_VALUE_SYNC);
  1227. if (rc < 0) {
  1228. dev_err(lpg->chip->dev, "Write LPG_PWM_SYNC failed, rc=%d\n",
  1229. rc);
  1230. return rc;
  1231. }
  1232. }
  1233. rc = qpnp_lpg_set_glitch_removal(lpg, true);
  1234. if (rc < 0) {
  1235. dev_err(lpg->chip->dev, "Enable glitch-removal failed, rc=%d\n",
  1236. rc);
  1237. return rc;
  1238. }
  1239. rc = qpnp_lpg_pwm_src_enable(lpg, true);
  1240. if (rc < 0)
  1241. dev_err(pwm_chip->dev, "Enable PWM output failed for channel %d, rc=%d\n",
  1242. lpg->lpg_idx, rc);
  1243. return rc;
  1244. }
  1245. static void qpnp_lpg_pwm_disable(struct pwm_chip *pwm_chip,
  1246. struct pwm_device *pwm)
  1247. {
  1248. struct qpnp_lpg_channel *lpg;
  1249. int rc;
  1250. lpg = pwm_dev_to_qpnp_lpg(pwm_chip, pwm);
  1251. if (lpg == NULL) {
  1252. dev_err(pwm_chip->dev, "lpg not found\n");
  1253. return;
  1254. }
  1255. rc = qpnp_lpg_pwm_src_enable(lpg, false);
  1256. if (rc < 0) {
  1257. dev_err(pwm_chip->dev, "Disable PWM output failed for channel %d, rc=%d\n",
  1258. lpg->lpg_idx, rc);
  1259. return;
  1260. }
  1261. rc = qpnp_lpg_set_glitch_removal(lpg, false);
  1262. if (rc < 0)
  1263. dev_err(lpg->chip->dev, "Disable glitch-removal failed, rc=%d\n",
  1264. rc);
  1265. }
  1266. static int qpnp_lpg_pwm_apply(struct pwm_chip *pwm_chip, struct pwm_device *pwm,
  1267. const struct pwm_state *state)
  1268. {
  1269. int rc;
  1270. if (state->period != pwm->state.period ||
  1271. state->duty_cycle != pwm->state.duty_cycle) {
  1272. rc = qpnp_lpg_pwm_config(pwm->chip, pwm,
  1273. state->duty_cycle, state->period);
  1274. if (rc < 0)
  1275. return rc;
  1276. pwm->state.duty_cycle = state->duty_cycle;
  1277. pwm->state.period = state->period;
  1278. }
  1279. if (state->enabled != pwm->state.enabled) {
  1280. if (state->enabled) {
  1281. rc = qpnp_lpg_pwm_enable(pwm->chip, pwm);
  1282. if (rc < 0)
  1283. return rc;
  1284. } else {
  1285. qpnp_lpg_pwm_disable(pwm->chip, pwm);
  1286. }
  1287. pwm->state.enabled = state->enabled;
  1288. }
  1289. return 0;
  1290. }
  1291. static const struct pwm_ops qpnp_lpg_pwm_ops = {
  1292. .apply = qpnp_lpg_pwm_apply,
  1293. .owner = THIS_MODULE,
  1294. };
  1295. static int qpnp_get_lpg_channels(struct qpnp_lpg_chip *chip, u32 *base)
  1296. {
  1297. int rc;
  1298. const __be32 *addr;
  1299. addr = of_get_address(chip->dev->of_node, 0, NULL, NULL);
  1300. if (!addr) {
  1301. dev_err(chip->dev, "Get %s address failed\n", LPG_BASE);
  1302. return -EINVAL;
  1303. }
  1304. *base = be32_to_cpu(addr[0]);
  1305. rc = of_property_read_u32(chip->dev->of_node, "qcom,num-lpg-channels",
  1306. &chip->num_lpgs);
  1307. if (rc < 0) {
  1308. dev_err(chip->dev, "Failed to get qcom,num-lpg-channels, rc=%d\n",
  1309. rc);
  1310. return rc;
  1311. }
  1312. if (chip->num_lpgs == 0) {
  1313. dev_err(chip->dev, "No LPG channels specified\n");
  1314. return -EINVAL;
  1315. }
  1316. return 0;
  1317. }
  1318. static int qpnp_lpg_parse_ramp_props_dt(struct device_node *node,
  1319. struct qpnp_lpg_chip *chip,
  1320. u32 lpg_chan_id, u32 max_count)
  1321. {
  1322. int rc;
  1323. u32 tmp;
  1324. struct qpnp_lpg_channel *lpg;
  1325. struct lpg_ramp_config *ramp;
  1326. /* lpg channel id is indexed from 1 in hardware */
  1327. lpg = &chip->lpgs[lpg_chan_id - 1];
  1328. ramp = &lpg->ramp_config;
  1329. rc = of_property_read_u32(node, "qcom,ramp-step-ms", &tmp);
  1330. if (rc < 0) {
  1331. dev_err(chip->dev, "get qcom,ramp-step-ms failed for lpg%d, rc=%d\n",
  1332. lpg_chan_id, rc);
  1333. return rc;
  1334. }
  1335. ramp->step_ms = (u16)tmp;
  1336. rc = of_property_read_u32(node, "qcom,ramp-low-index", &tmp);
  1337. if (rc < 0) {
  1338. dev_err(chip->dev, "get qcom,ramp-low-index failed for lpg%d, rc=%d\n",
  1339. lpg_chan_id, rc);
  1340. return rc;
  1341. }
  1342. ramp->lo_idx = (u8)tmp;
  1343. if (ramp->lo_idx >= max_count) {
  1344. dev_err(chip->dev, "qcom,ramp-low-index should less than max %d\n",
  1345. max_count);
  1346. return -EINVAL;
  1347. }
  1348. rc = of_property_read_u32(node, "qcom,ramp-high-index", &tmp);
  1349. if (rc < 0) {
  1350. dev_err(chip->dev, "get qcom,ramp-high-index failed for lpg%d, rc=%d\n",
  1351. lpg_chan_id, rc);
  1352. return rc;
  1353. }
  1354. ramp->hi_idx = (u8)tmp;
  1355. if (ramp->hi_idx > max_count) {
  1356. dev_err(chip->dev, "qcom,ramp-high-index shouldn't exceed max %d\n",
  1357. max_count);
  1358. return -EINVAL;
  1359. }
  1360. if (chip->use_sdam && ramp->hi_idx <= ramp->lo_idx) {
  1361. dev_err(chip->dev, "high-index(%d) should be larger than low-index(%d) when SDAM used\n",
  1362. ramp->hi_idx, ramp->lo_idx);
  1363. return -EINVAL;
  1364. }
  1365. ramp->pattern_length = ramp->hi_idx - ramp->lo_idx + 1;
  1366. ramp->pattern = &chip->lut->pattern[ramp->lo_idx];
  1367. lpg->max_pattern_length = ramp->pattern_length;
  1368. ramp->pattern_repeat = of_property_read_bool(node,
  1369. "qcom,ramp-pattern-repeat");
  1370. ramp->pause_hi_count = 0;
  1371. rc = of_property_read_u32(node, "qcom,ramp-pause-hi-count", &tmp);
  1372. if (!rc) {
  1373. if (chip->use_sdam && tmp > SDAM_PAUSE_COUNT_MAX)
  1374. return -EINVAL;
  1375. ramp->pause_hi_count = (u8)tmp;
  1376. }
  1377. ramp->pause_lo_count = 0;
  1378. rc = of_property_read_u32(node, "qcom,ramp-pause-lo-count", &tmp);
  1379. if (!rc) {
  1380. if (chip->use_sdam && tmp > SDAM_PAUSE_COUNT_MAX)
  1381. return -EINVAL;
  1382. ramp->pause_lo_count = (u8)tmp;
  1383. }
  1384. if (chip->use_sdam)
  1385. return 0;
  1386. ramp->ramp_dir_low_to_hi = of_property_read_bool(node,
  1387. "qcom,ramp-from-low-to-high");
  1388. ramp->toggle = of_property_read_bool(node, "qcom,ramp-toggle");
  1389. return rc;
  1390. }
  1391. static int qpnp_lpg_parse_pattern_dt(struct qpnp_lpg_chip *chip,
  1392. u32 max_count)
  1393. {
  1394. struct device_node *child;
  1395. struct qpnp_lpg_channel *lpg;
  1396. struct lpg_ramp_config *ramp;
  1397. int rc = 0, i;
  1398. u32 length, lpg_chan_id, tmp;
  1399. chip->lut->chip = chip;
  1400. mutex_init(&chip->lut->lock);
  1401. rc = of_property_count_elems_of_size(chip->dev->of_node,
  1402. "qcom,lut-patterns", sizeof(u32));
  1403. if (rc < 0) {
  1404. dev_err(chip->dev, "Read qcom,lut-patterns failed, rc=%d\n",
  1405. rc);
  1406. return rc;
  1407. }
  1408. length = rc;
  1409. if (length > max_count) {
  1410. dev_err(chip->dev, "qcom,lut-patterns length %d exceed max %d\n",
  1411. length, max_count);
  1412. return -EINVAL;
  1413. }
  1414. chip->lut->pattern = devm_kcalloc(chip->dev, max_count,
  1415. sizeof(*chip->lut->pattern), GFP_KERNEL);
  1416. if (!chip->lut->pattern)
  1417. return -ENOMEM;
  1418. rc = of_property_read_u32_array(chip->dev->of_node, "qcom,lut-patterns",
  1419. chip->lut->pattern, length);
  1420. if (rc < 0) {
  1421. dev_err(chip->dev, "Get qcom,lut-patterns failed, rc=%d\n",
  1422. rc);
  1423. return rc;
  1424. }
  1425. if (of_get_available_child_count(chip->dev->of_node) == 0) {
  1426. dev_err(chip->dev, "No ramp configuration for any LPG\n");
  1427. return -EINVAL;
  1428. }
  1429. for_each_available_child_of_node(chip->dev->of_node, child) {
  1430. rc = of_property_read_u32(child, "qcom,lpg-chan-id",
  1431. &lpg_chan_id);
  1432. if (rc < 0) {
  1433. dev_err(chip->dev, "Get qcom,lpg-chan-id failed for node %s, rc=%d\n",
  1434. child->name, rc);
  1435. return rc;
  1436. }
  1437. if (lpg_chan_id < 1 || lpg_chan_id > chip->num_lpgs) {
  1438. dev_err(chip->dev, "lpg-chann-id %d is out of range 1~%d\n",
  1439. lpg_chan_id, chip->num_lpgs);
  1440. return -EINVAL;
  1441. }
  1442. if (chip->lpgs[lpg_chan_id - 1].enable_pfm) {
  1443. dev_err(chip->dev, "Cannot configure ramp for PFM-enabled channel %d\n",
  1444. lpg_chan_id);
  1445. return -EINVAL;
  1446. }
  1447. if (chip->use_sdam) {
  1448. rc = of_property_read_u32(child,
  1449. "qcom,lpg-sdam-base",
  1450. &tmp);
  1451. if (rc < 0) {
  1452. dev_err(chip->dev, "get qcom,lpg-sdam-base failed for lpg%d, rc=%d\n",
  1453. lpg_chan_id, rc);
  1454. return rc;
  1455. }
  1456. chip->lpgs[lpg_chan_id - 1].lpg_sdam_base = tmp;
  1457. }
  1458. rc = qpnp_lpg_parse_ramp_props_dt(child, chip, lpg_chan_id,
  1459. max_count);
  1460. if (rc) {
  1461. dev_err(chip->dev, "Parsing ramp props failed for lpg%d, rc=%d\n",
  1462. lpg_chan_id, rc);
  1463. return rc;
  1464. }
  1465. }
  1466. rc = of_property_count_elems_of_size(chip->dev->of_node,
  1467. "qcom,sync-channel-ids", sizeof(u32));
  1468. if (rc < 0)
  1469. return 0;
  1470. length = rc;
  1471. if (length > chip->num_lpgs) {
  1472. dev_err(chip->dev, "qcom,sync-channel-ids has too many channels: %d\n",
  1473. length);
  1474. return -EINVAL;
  1475. }
  1476. chip->lpg_group = devm_kcalloc(chip->dev, chip->num_lpgs,
  1477. sizeof(u32), GFP_KERNEL);
  1478. if (!chip->lpg_group)
  1479. return -ENOMEM;
  1480. rc = of_property_read_u32_array(chip->dev->of_node,
  1481. "qcom,sync-channel-ids", chip->lpg_group, length);
  1482. if (rc < 0) {
  1483. dev_err(chip->dev, "Get qcom,sync-channel-ids failed, rc=%d\n",
  1484. rc);
  1485. return rc;
  1486. }
  1487. for (i = 0; i < length; i++) {
  1488. if (chip->lpg_group[i] <= 0 ||
  1489. chip->lpg_group[i] > chip->num_lpgs) {
  1490. dev_err(chip->dev, "lpg_group[%d]: %d is not a valid channel\n",
  1491. i, chip->lpg_group[i]);
  1492. return -EINVAL;
  1493. }
  1494. }
  1495. /*
  1496. * The LPG channel in the same group should have the same ramping
  1497. * configuration, so force to use the ramping configuration of the
  1498. * 1st LPG channel in the group for synchronization.
  1499. */
  1500. lpg = &chip->lpgs[chip->lpg_group[0] - 1];
  1501. ramp = &lpg->ramp_config;
  1502. for (i = 1; i < length; i++) {
  1503. lpg = &chip->lpgs[chip->lpg_group[i] - 1];
  1504. memcpy(&lpg->ramp_config, ramp, sizeof(struct lpg_ramp_config));
  1505. }
  1506. return 0;
  1507. }
  1508. static bool lut_is_defined(struct qpnp_lpg_chip *chip, const __be32 **addr)
  1509. {
  1510. *addr = of_get_address(chip->dev->of_node, 1, NULL, NULL);
  1511. if (*addr == NULL)
  1512. return false;
  1513. return true;
  1514. }
  1515. static int qpnp_lpg_get_nvmem_dt(struct qpnp_lpg_chip *chip)
  1516. {
  1517. int rc = 0;
  1518. struct nvmem_device *ppg_nv, *lut_nv, *lpg_nv;
  1519. /* Ensure backward compatibility */
  1520. ppg_nv = devm_nvmem_device_get(chip->dev, "ppg_sdam");
  1521. if (IS_ERR(ppg_nv)) {
  1522. lut_nv = devm_nvmem_device_get(chip->dev, "lut_sdam");
  1523. if (IS_ERR(lut_nv)) {
  1524. rc = PTR_ERR(lut_nv);
  1525. goto err;
  1526. }
  1527. lpg_nv = devm_nvmem_device_get(chip->dev, "lpg_chan_sdam");
  1528. if (IS_ERR(lpg_nv)) {
  1529. rc = PTR_ERR(lpg_nv);
  1530. goto err;
  1531. }
  1532. chip->lut_nvmem = lut_nv;
  1533. chip->lpg_chan_nvmem = lpg_nv;
  1534. chip->lut->nvmem_count = PPG_NVMEMS_2;
  1535. } else {
  1536. chip->lut_nvmem = chip->lpg_chan_nvmem = ppg_nv;
  1537. chip->lut->nvmem_count = PPG_NVMEMS_1;
  1538. }
  1539. return 0;
  1540. err:
  1541. if (rc != -EPROBE_DEFER)
  1542. dev_err(chip->dev, "Failed to get nvmem device, rc=%d\n",
  1543. rc);
  1544. return rc;
  1545. }
  1546. static int qpnp_lpg_parse_pfm_support(struct qpnp_lpg_chip *chip)
  1547. {
  1548. u32 chan_idx;
  1549. u32 num_pfm_channels;
  1550. u8 val;
  1551. int i, rc;
  1552. rc = of_property_count_elems_of_size(chip->dev->of_node,
  1553. "qcom,pfm-chan-ids",
  1554. sizeof(u32));
  1555. if (rc < 0)
  1556. return rc;
  1557. if (rc == 0 || rc > chip->num_lpgs)
  1558. return -EINVAL;
  1559. num_pfm_channels = rc;
  1560. for (i = 0; i < num_pfm_channels; i++) {
  1561. rc = of_property_read_u32_index(chip->dev->of_node,
  1562. "qcom,pfm-chan-ids", i, &chan_idx);
  1563. if (rc) {
  1564. dev_err(chip->dev, "Read pfm channel %d failed, rc=%d\n",
  1565. i, rc);
  1566. return -EINVAL;
  1567. }
  1568. if (chan_idx < 1 || chan_idx > chip->num_lpgs) {
  1569. dev_err(chip->dev, "pfm chan id %u is out of range 1~%d\n",
  1570. chan_idx, chip->num_lpgs);
  1571. return -EINVAL;
  1572. }
  1573. chan_idx--; /* zero-based indexing */
  1574. if (chip->lpgs[chan_idx].subtype == SUBTYPE_PWM ||
  1575. chip->lpgs[chan_idx].subtype == SUBTYPE_HI_RES_PWM) {
  1576. rc = qpnp_lpg_read(&chip->lpgs[chan_idx],
  1577. REG_PWM_STATUS1, &val);
  1578. if (rc < 0) {
  1579. dev_err(chip->dev, "Read status1 failed, rc=%d\n",
  1580. rc);
  1581. return rc;
  1582. }
  1583. if (val & FM_MODE_PRESENT)
  1584. chip->lpgs[chan_idx].enable_pfm = true;
  1585. else
  1586. return -EOPNOTSUPP;
  1587. }
  1588. }
  1589. return rc;
  1590. }
  1591. #define DEFAULT_TICK_DURATION_US 7800
  1592. static int qpnp_lpg_parse_dt(struct qpnp_lpg_chip *chip)
  1593. {
  1594. int rc = 0, i;
  1595. u32 base;
  1596. const __be32 *addr;
  1597. rc = qpnp_get_lpg_channels(chip, &base);
  1598. if (rc < 0)
  1599. return rc;
  1600. chip->lpgs = devm_kcalloc(chip->dev, chip->num_lpgs,
  1601. sizeof(*chip->lpgs), GFP_KERNEL);
  1602. if (!chip->lpgs)
  1603. return -ENOMEM;
  1604. for (i = 0; i < chip->num_lpgs; i++) {
  1605. chip->lpgs[i].chip = chip;
  1606. chip->lpgs[i].lpg_idx = i;
  1607. chip->lpgs[i].reg_base = base + i * REG_SIZE_PER_LPG;
  1608. chip->lpgs[i].src_sel = PWM_VALUE;
  1609. rc = qpnp_lpg_read(&chip->lpgs[i], REG_LPG_PERPH_SUBTYPE,
  1610. &chip->lpgs[i].subtype);
  1611. if (rc < 0) {
  1612. dev_err(chip->dev, "Read subtype failed, rc=%d\n", rc);
  1613. return rc;
  1614. }
  1615. }
  1616. if (of_find_property(chip->dev->of_node,
  1617. "qcom,pfm-chan-ids", NULL)) {
  1618. rc = qpnp_lpg_parse_pfm_support(chip);
  1619. if (rc < 0) {
  1620. dev_err(chip->dev, "PFM channels specified incorrectly\n");
  1621. return rc;
  1622. }
  1623. }
  1624. if (of_find_property(chip->dev->of_node, "nvmem", NULL)) {
  1625. chip->lut = devm_kmalloc(chip->dev, sizeof(*chip->lut),
  1626. GFP_KERNEL);
  1627. if (!chip->lut)
  1628. return -ENOMEM;
  1629. rc = qpnp_lpg_get_nvmem_dt(chip);
  1630. if (rc < 0)
  1631. return rc;
  1632. chip->use_sdam = true;
  1633. if (of_find_property(chip->dev->of_node, "qcom,pbs-client",
  1634. NULL)) {
  1635. chip->pbs_dev_node = of_parse_phandle(
  1636. chip->dev->of_node,
  1637. "qcom,pbs-client", 0);
  1638. if (!chip->pbs_dev_node) {
  1639. dev_err(chip->dev, "Missing qcom,pbs-client property\n");
  1640. return -ENODEV;
  1641. }
  1642. }
  1643. rc = of_property_read_u32(chip->dev->of_node,
  1644. "qcom,lut-sdam-base", &chip->lut->reg_base);
  1645. if (rc < 0) {
  1646. dev_err(chip->dev, "Read qcom,lut-sdam-base failed, rc=%d\n",
  1647. rc);
  1648. of_node_put(chip->pbs_dev_node);
  1649. return rc;
  1650. }
  1651. chip->lut->ramp_step_tick_us = DEFAULT_TICK_DURATION_US;
  1652. of_property_read_u32(chip->dev->of_node, "qcom,tick-duration-us",
  1653. &chip->lut->ramp_step_tick_us);
  1654. rc = qpnp_lpg_parse_pattern_dt(chip, SDAM_LUT_COUNT_MAX);
  1655. if (rc < 0) {
  1656. of_node_put(chip->pbs_dev_node);
  1657. return rc;
  1658. }
  1659. } else if (lut_is_defined(chip, &addr)) {
  1660. chip->lut = devm_kmalloc(chip->dev, sizeof(*chip->lut),
  1661. GFP_KERNEL);
  1662. if (!chip->lut)
  1663. return -ENOMEM;
  1664. chip->lut->reg_base = be32_to_cpu(*addr);
  1665. rc = qpnp_lpg_parse_pattern_dt(chip, LPG_LUT_COUNT_MAX);
  1666. if (rc < 0)
  1667. return rc;
  1668. } else {
  1669. pr_debug("Neither SDAM nor LUT specified\n");
  1670. }
  1671. return 0;
  1672. }
  1673. static int qpnp_lpg_sdam_hw_init(struct qpnp_lpg_chip *chip)
  1674. {
  1675. struct qpnp_lpg_channel *lpg;
  1676. int i, rc = 0;
  1677. if (!chip->use_sdam)
  1678. return 0;
  1679. for (i = 0; i < chip->num_lpgs; i++) {
  1680. lpg = &chip->lpgs[i];
  1681. if (lpg->lpg_sdam_base != 0) {
  1682. rc = qpnp_lpg_sdam_write(lpg, SDAM_LUT_EN_OFFSET, 0);
  1683. if (rc < 0) {
  1684. dev_err(chip->dev, "Write SDAM_REG_LUT_EN failed, rc=%d\n",
  1685. rc);
  1686. return rc;
  1687. }
  1688. rc = qpnp_lpg_sdam_write(lpg,
  1689. SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET, 0);
  1690. if (rc < 0) {
  1691. dev_err(lpg->chip->dev, "Write SDAM_REG_PBS_SCRATCH_LUT_COUNTER failed, rc=%d\n",
  1692. rc);
  1693. return rc;
  1694. }
  1695. }
  1696. }
  1697. return rc;
  1698. }
  1699. static int qpnp_lpg_probe(struct platform_device *pdev)
  1700. {
  1701. int rc, i;
  1702. struct qpnp_lpg_chip *chip;
  1703. struct qpnp_lpg_channel *lpg;
  1704. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  1705. if (!chip)
  1706. return -ENOMEM;
  1707. chip->dev = &pdev->dev;
  1708. chip->regmap = dev_get_regmap(chip->dev->parent, NULL);
  1709. if (!chip->regmap) {
  1710. dev_err(chip->dev, "Getting regmap failed\n");
  1711. return -EINVAL;
  1712. }
  1713. mutex_init(&chip->bus_lock);
  1714. rc = qpnp_lpg_parse_dt(chip);
  1715. if (rc < 0) {
  1716. if (rc != -EPROBE_DEFER)
  1717. dev_err(chip->dev, "Devicetree properties parsing failed, rc=%d\n",
  1718. rc);
  1719. goto err_out;
  1720. }
  1721. rc = qpnp_lpg_sdam_hw_init(chip);
  1722. if (rc < 0) {
  1723. dev_err(chip->dev, "SDAM HW init failed, rc=%d\n",
  1724. rc);
  1725. goto err_out;
  1726. }
  1727. for (i = 0; i < chip->num_lpgs; i++) {
  1728. lpg = &chip->lpgs[i];
  1729. lpg->output_type = PWM_OUTPUT_FIXED;
  1730. if (chip->lut != NULL) {
  1731. rc = qpnp_lpg_pwm_src_enable(lpg, false);
  1732. if (rc < 0) {
  1733. dev_err(chip->dev, "Disable PWM output failed for channel %d, rc=%d\n",
  1734. lpg->lpg_idx, rc);
  1735. return rc;
  1736. }
  1737. }
  1738. if (lpg->enable_pfm) {
  1739. rc = qpnp_lpg_write(lpg, REG_PWM_FM_MODE,
  1740. FM_MODE_ENABLE);
  1741. if (rc < 0) {
  1742. dev_err(chip->dev, "Write fm_mode_enable failed, rc=%d\n",
  1743. rc);
  1744. return rc;
  1745. }
  1746. }
  1747. }
  1748. dev_set_drvdata(chip->dev, chip);
  1749. chip->pwm_chip.dev = chip->dev;
  1750. chip->pwm_chip.base = -1;
  1751. chip->pwm_chip.npwm = chip->num_lpgs;
  1752. chip->pwm_chip.ops = &qpnp_lpg_pwm_ops;
  1753. rc = pwmchip_add(&chip->pwm_chip);
  1754. if (rc < 0) {
  1755. dev_err(chip->dev, "Add pwmchip failed, rc=%d\n", rc);
  1756. goto err_out;
  1757. }
  1758. return 0;
  1759. err_out:
  1760. mutex_destroy(&chip->bus_lock);
  1761. return rc;
  1762. }
  1763. static int qpnp_lpg_remove(struct platform_device *pdev)
  1764. {
  1765. struct qpnp_lpg_chip *chip = dev_get_drvdata(&pdev->dev);
  1766. of_node_put(chip->pbs_dev_node);
  1767. pwmchip_remove(&chip->pwm_chip);
  1768. mutex_destroy(&chip->bus_lock);
  1769. dev_set_drvdata(chip->dev, NULL);
  1770. return 0;
  1771. }
  1772. static const struct of_device_id qpnp_lpg_of_match[] = {
  1773. { .compatible = "qcom,pwm-lpg",},
  1774. { },
  1775. };
  1776. static struct platform_driver qpnp_lpg_driver = {
  1777. .driver = {
  1778. .name = "qcom,pwm-lpg",
  1779. .of_match_table = qpnp_lpg_of_match,
  1780. },
  1781. .probe = qpnp_lpg_probe,
  1782. .remove = qpnp_lpg_remove,
  1783. };
  1784. module_platform_driver(qpnp_lpg_driver);
  1785. MODULE_DESCRIPTION("QTI LPG driver");
  1786. MODULE_LICENSE("GPL v2");
  1787. MODULE_ALIAS("pwm:pwm-lpg");