gpio-mvebu.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GPIO driver for Marvell SoCs
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Thomas Petazzoni <[email protected]>
  8. * Andrew Lunn <[email protected]>
  9. * Sebastian Hesselbarth <[email protected]>
  10. *
  11. * This driver is a fairly straightforward GPIO driver for the
  12. * complete family of Marvell EBU SoC platforms (Orion, Dove,
  13. * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
  14. * driver is the different register layout that exists between the
  15. * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
  16. * platforms (MV78200 from the Discovery family and the Armada
  17. * XP). Therefore, this driver handles three variants of the GPIO
  18. * block:
  19. * - the basic variant, called "orion-gpio", with the simplest
  20. * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
  21. * non-SMP Discovery systems
  22. * - the mv78200 variant for MV78200 Discovery systems. This variant
  23. * turns the edge mask and level mask registers into CPU0 edge
  24. * mask/level mask registers, and adds CPU1 edge mask/level mask
  25. * registers.
  26. * - the armadaxp variant for Armada XP systems. This variant keeps
  27. * the normal cause/edge mask/level mask registers when the global
  28. * interrupts are used, but adds per-CPU cause/edge mask/level mask
  29. * registers n a separate memory area for the per-CPU GPIO
  30. * interrupts.
  31. */
  32. #include <linux/bitops.h>
  33. #include <linux/clk.h>
  34. #include <linux/err.h>
  35. #include <linux/gpio/driver.h>
  36. #include <linux/gpio/consumer.h>
  37. #include <linux/gpio/machine.h>
  38. #include <linux/init.h>
  39. #include <linux/io.h>
  40. #include <linux/irq.h>
  41. #include <linux/irqchip/chained_irq.h>
  42. #include <linux/irqdomain.h>
  43. #include <linux/mfd/syscon.h>
  44. #include <linux/of_device.h>
  45. #include <linux/pinctrl/consumer.h>
  46. #include <linux/platform_device.h>
  47. #include <linux/pwm.h>
  48. #include <linux/regmap.h>
  49. #include <linux/slab.h>
  50. /*
  51. * GPIO unit register offsets.
  52. */
  53. #define GPIO_OUT_OFF 0x0000
  54. #define GPIO_IO_CONF_OFF 0x0004
  55. #define GPIO_BLINK_EN_OFF 0x0008
  56. #define GPIO_IN_POL_OFF 0x000c
  57. #define GPIO_DATA_IN_OFF 0x0010
  58. #define GPIO_EDGE_CAUSE_OFF 0x0014
  59. #define GPIO_EDGE_MASK_OFF 0x0018
  60. #define GPIO_LEVEL_MASK_OFF 0x001c
  61. #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
  62. /*
  63. * PWM register offsets.
  64. */
  65. #define PWM_BLINK_ON_DURATION_OFF 0x0
  66. #define PWM_BLINK_OFF_DURATION_OFF 0x4
  67. #define PWM_BLINK_COUNTER_B_OFF 0x8
  68. /* Armada 8k variant gpios register offsets */
  69. #define AP80X_GPIO0_OFF_A8K 0x1040
  70. #define CP11X_GPIO0_OFF_A8K 0x100
  71. #define CP11X_GPIO1_OFF_A8K 0x140
  72. /* The MV78200 has per-CPU registers for edge mask and level mask */
  73. #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
  74. #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
  75. /*
  76. * The Armada XP has per-CPU registers for interrupt cause, interrupt
  77. * mask and interrupt level mask. Those are in percpu_regs range.
  78. */
  79. #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
  80. #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
  81. #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
  82. #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
  83. #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
  84. #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
  85. #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
  86. #define MVEBU_MAX_GPIO_PER_BANK 32
  87. struct mvebu_pwm {
  88. struct regmap *regs;
  89. u32 offset;
  90. unsigned long clk_rate;
  91. struct gpio_desc *gpiod;
  92. struct pwm_chip chip;
  93. spinlock_t lock;
  94. struct mvebu_gpio_chip *mvchip;
  95. /* Used to preserve GPIO/PWM registers across suspend/resume */
  96. u32 blink_select;
  97. u32 blink_on_duration;
  98. u32 blink_off_duration;
  99. };
  100. struct mvebu_gpio_chip {
  101. struct gpio_chip chip;
  102. struct regmap *regs;
  103. u32 offset;
  104. struct regmap *percpu_regs;
  105. int irqbase;
  106. struct irq_domain *domain;
  107. int soc_variant;
  108. /* Used for PWM support */
  109. struct clk *clk;
  110. struct mvebu_pwm *mvpwm;
  111. /* Used to preserve GPIO registers across suspend/resume */
  112. u32 out_reg;
  113. u32 io_conf_reg;
  114. u32 blink_en_reg;
  115. u32 in_pol_reg;
  116. u32 edge_mask_regs[4];
  117. u32 level_mask_regs[4];
  118. };
  119. /*
  120. * Functions returning addresses of individual registers for a given
  121. * GPIO controller.
  122. */
  123. static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
  124. struct regmap **map, unsigned int *offset)
  125. {
  126. int cpu;
  127. switch (mvchip->soc_variant) {
  128. case MVEBU_GPIO_SOC_VARIANT_ORION:
  129. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  130. case MVEBU_GPIO_SOC_VARIANT_A8K:
  131. *map = mvchip->regs;
  132. *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
  133. break;
  134. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  135. cpu = smp_processor_id();
  136. *map = mvchip->percpu_regs;
  137. *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
  138. break;
  139. default:
  140. BUG();
  141. }
  142. }
  143. static u32
  144. mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
  145. {
  146. struct regmap *map;
  147. unsigned int offset;
  148. u32 val;
  149. mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
  150. regmap_read(map, offset, &val);
  151. return val;
  152. }
  153. static void
  154. mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
  155. {
  156. struct regmap *map;
  157. unsigned int offset;
  158. mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
  159. regmap_write(map, offset, val);
  160. }
  161. static inline void
  162. mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
  163. struct regmap **map, unsigned int *offset)
  164. {
  165. int cpu;
  166. switch (mvchip->soc_variant) {
  167. case MVEBU_GPIO_SOC_VARIANT_ORION:
  168. case MVEBU_GPIO_SOC_VARIANT_A8K:
  169. *map = mvchip->regs;
  170. *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
  171. break;
  172. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  173. cpu = smp_processor_id();
  174. *map = mvchip->regs;
  175. *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
  176. break;
  177. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  178. cpu = smp_processor_id();
  179. *map = mvchip->percpu_regs;
  180. *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
  181. break;
  182. default:
  183. BUG();
  184. }
  185. }
  186. static u32
  187. mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
  188. {
  189. struct regmap *map;
  190. unsigned int offset;
  191. u32 val;
  192. mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
  193. regmap_read(map, offset, &val);
  194. return val;
  195. }
  196. static void
  197. mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
  198. {
  199. struct regmap *map;
  200. unsigned int offset;
  201. mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
  202. regmap_write(map, offset, val);
  203. }
  204. static void
  205. mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
  206. struct regmap **map, unsigned int *offset)
  207. {
  208. int cpu;
  209. switch (mvchip->soc_variant) {
  210. case MVEBU_GPIO_SOC_VARIANT_ORION:
  211. case MVEBU_GPIO_SOC_VARIANT_A8K:
  212. *map = mvchip->regs;
  213. *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
  214. break;
  215. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  216. cpu = smp_processor_id();
  217. *map = mvchip->regs;
  218. *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
  219. break;
  220. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  221. cpu = smp_processor_id();
  222. *map = mvchip->percpu_regs;
  223. *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
  224. break;
  225. default:
  226. BUG();
  227. }
  228. }
  229. static u32
  230. mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
  231. {
  232. struct regmap *map;
  233. unsigned int offset;
  234. u32 val;
  235. mvebu_gpioreg_level_mask(mvchip, &map, &offset);
  236. regmap_read(map, offset, &val);
  237. return val;
  238. }
  239. static void
  240. mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
  241. {
  242. struct regmap *map;
  243. unsigned int offset;
  244. mvebu_gpioreg_level_mask(mvchip, &map, &offset);
  245. regmap_write(map, offset, val);
  246. }
  247. /*
  248. * Functions returning offsets of individual registers for a given
  249. * PWM controller.
  250. */
  251. static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
  252. {
  253. return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
  254. }
  255. static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
  256. {
  257. return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
  258. }
  259. /*
  260. * Functions implementing the gpio_chip methods
  261. */
  262. static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
  263. {
  264. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  265. regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
  266. BIT(pin), value ? BIT(pin) : 0);
  267. }
  268. static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
  269. {
  270. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  271. u32 u;
  272. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
  273. if (u & BIT(pin)) {
  274. u32 data_in, in_pol;
  275. regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
  276. &data_in);
  277. regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
  278. &in_pol);
  279. u = data_in ^ in_pol;
  280. } else {
  281. regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
  282. }
  283. return (u >> pin) & 1;
  284. }
  285. static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
  286. int value)
  287. {
  288. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  289. regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
  290. BIT(pin), value ? BIT(pin) : 0);
  291. }
  292. static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
  293. {
  294. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  295. int ret;
  296. /*
  297. * Check with the pinctrl driver whether this pin is usable as
  298. * an input GPIO
  299. */
  300. ret = pinctrl_gpio_direction_input(chip->base + pin);
  301. if (ret)
  302. return ret;
  303. regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
  304. BIT(pin), BIT(pin));
  305. return 0;
  306. }
  307. static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
  308. int value)
  309. {
  310. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  311. int ret;
  312. /*
  313. * Check with the pinctrl driver whether this pin is usable as
  314. * an output GPIO
  315. */
  316. ret = pinctrl_gpio_direction_output(chip->base + pin);
  317. if (ret)
  318. return ret;
  319. mvebu_gpio_blink(chip, pin, 0);
  320. mvebu_gpio_set(chip, pin, value);
  321. regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
  322. BIT(pin), 0);
  323. return 0;
  324. }
  325. static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
  326. {
  327. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  328. u32 u;
  329. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
  330. if (u & BIT(pin))
  331. return GPIO_LINE_DIRECTION_IN;
  332. return GPIO_LINE_DIRECTION_OUT;
  333. }
  334. static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
  335. {
  336. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  337. return irq_create_mapping(mvchip->domain, pin);
  338. }
  339. /*
  340. * Functions implementing the irq_chip methods
  341. */
  342. static void mvebu_gpio_irq_ack(struct irq_data *d)
  343. {
  344. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  345. struct mvebu_gpio_chip *mvchip = gc->private;
  346. u32 mask = d->mask;
  347. irq_gc_lock(gc);
  348. mvebu_gpio_write_edge_cause(mvchip, ~mask);
  349. irq_gc_unlock(gc);
  350. }
  351. static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
  352. {
  353. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  354. struct mvebu_gpio_chip *mvchip = gc->private;
  355. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  356. u32 mask = d->mask;
  357. irq_gc_lock(gc);
  358. ct->mask_cache_priv &= ~mask;
  359. mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
  360. irq_gc_unlock(gc);
  361. }
  362. static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
  363. {
  364. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  365. struct mvebu_gpio_chip *mvchip = gc->private;
  366. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  367. u32 mask = d->mask;
  368. irq_gc_lock(gc);
  369. mvebu_gpio_write_edge_cause(mvchip, ~mask);
  370. ct->mask_cache_priv |= mask;
  371. mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
  372. irq_gc_unlock(gc);
  373. }
  374. static void mvebu_gpio_level_irq_mask(struct irq_data *d)
  375. {
  376. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  377. struct mvebu_gpio_chip *mvchip = gc->private;
  378. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  379. u32 mask = d->mask;
  380. irq_gc_lock(gc);
  381. ct->mask_cache_priv &= ~mask;
  382. mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
  383. irq_gc_unlock(gc);
  384. }
  385. static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
  386. {
  387. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  388. struct mvebu_gpio_chip *mvchip = gc->private;
  389. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  390. u32 mask = d->mask;
  391. irq_gc_lock(gc);
  392. ct->mask_cache_priv |= mask;
  393. mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
  394. irq_gc_unlock(gc);
  395. }
  396. /*****************************************************************************
  397. * MVEBU GPIO IRQ
  398. *
  399. * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
  400. * value of the line or the opposite value.
  401. *
  402. * Level IRQ handlers: DATA_IN is used directly as cause register.
  403. * Interrupt are masked by LEVEL_MASK registers.
  404. * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
  405. * Interrupt are masked by EDGE_MASK registers.
  406. * Both-edge handlers: Similar to regular Edge handlers, but also swaps
  407. * the polarity to catch the next line transaction.
  408. * This is a race condition that might not perfectly
  409. * work on some use cases.
  410. *
  411. * Every eight GPIO lines are grouped (OR'ed) before going up to main
  412. * cause register.
  413. *
  414. * EDGE cause mask
  415. * data-in /--------| |-----| |----\
  416. * -----| |----- ---- to main cause reg
  417. * X \----------------| |----/
  418. * polarity LEVEL mask
  419. *
  420. ****************************************************************************/
  421. static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  422. {
  423. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  424. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  425. struct mvebu_gpio_chip *mvchip = gc->private;
  426. int pin;
  427. u32 u;
  428. pin = d->hwirq;
  429. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
  430. if ((u & BIT(pin)) == 0)
  431. return -EINVAL;
  432. type &= IRQ_TYPE_SENSE_MASK;
  433. if (type == IRQ_TYPE_NONE)
  434. return -EINVAL;
  435. /* Check if we need to change chip and handler */
  436. if (!(ct->type & type))
  437. if (irq_setup_alt_chip(d, type))
  438. return -EINVAL;
  439. /*
  440. * Configure interrupt polarity.
  441. */
  442. switch (type) {
  443. case IRQ_TYPE_EDGE_RISING:
  444. case IRQ_TYPE_LEVEL_HIGH:
  445. regmap_update_bits(mvchip->regs,
  446. GPIO_IN_POL_OFF + mvchip->offset,
  447. BIT(pin), 0);
  448. break;
  449. case IRQ_TYPE_EDGE_FALLING:
  450. case IRQ_TYPE_LEVEL_LOW:
  451. regmap_update_bits(mvchip->regs,
  452. GPIO_IN_POL_OFF + mvchip->offset,
  453. BIT(pin), BIT(pin));
  454. break;
  455. case IRQ_TYPE_EDGE_BOTH: {
  456. u32 data_in, in_pol, val;
  457. regmap_read(mvchip->regs,
  458. GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
  459. regmap_read(mvchip->regs,
  460. GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
  461. /*
  462. * set initial polarity based on current input level
  463. */
  464. if ((data_in ^ in_pol) & BIT(pin))
  465. val = BIT(pin); /* falling */
  466. else
  467. val = 0; /* raising */
  468. regmap_update_bits(mvchip->regs,
  469. GPIO_IN_POL_OFF + mvchip->offset,
  470. BIT(pin), val);
  471. break;
  472. }
  473. }
  474. return 0;
  475. }
  476. static void mvebu_gpio_irq_handler(struct irq_desc *desc)
  477. {
  478. struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
  479. struct irq_chip *chip = irq_desc_get_chip(desc);
  480. u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
  481. int i;
  482. if (mvchip == NULL)
  483. return;
  484. chained_irq_enter(chip, desc);
  485. regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
  486. level_mask = mvebu_gpio_read_level_mask(mvchip);
  487. edge_cause = mvebu_gpio_read_edge_cause(mvchip);
  488. edge_mask = mvebu_gpio_read_edge_mask(mvchip);
  489. cause = (data_in & level_mask) | (edge_cause & edge_mask);
  490. for (i = 0; i < mvchip->chip.ngpio; i++) {
  491. int irq;
  492. irq = irq_find_mapping(mvchip->domain, i);
  493. if (!(cause & BIT(i)))
  494. continue;
  495. type = irq_get_trigger_type(irq);
  496. if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
  497. /* Swap polarity (race with GPIO line) */
  498. u32 polarity;
  499. regmap_read(mvchip->regs,
  500. GPIO_IN_POL_OFF + mvchip->offset,
  501. &polarity);
  502. polarity ^= BIT(i);
  503. regmap_write(mvchip->regs,
  504. GPIO_IN_POL_OFF + mvchip->offset,
  505. polarity);
  506. }
  507. generic_handle_irq(irq);
  508. }
  509. chained_irq_exit(chip, desc);
  510. }
  511. static const struct regmap_config mvebu_gpio_regmap_config = {
  512. .reg_bits = 32,
  513. .reg_stride = 4,
  514. .val_bits = 32,
  515. .fast_io = true,
  516. };
  517. /*
  518. * Functions implementing the pwm_chip methods
  519. */
  520. static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
  521. {
  522. return container_of(chip, struct mvebu_pwm, chip);
  523. }
  524. static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  525. {
  526. struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
  527. struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
  528. struct gpio_desc *desc;
  529. unsigned long flags;
  530. int ret = 0;
  531. spin_lock_irqsave(&mvpwm->lock, flags);
  532. if (mvpwm->gpiod) {
  533. ret = -EBUSY;
  534. } else {
  535. desc = gpiochip_request_own_desc(&mvchip->chip,
  536. pwm->hwpwm, "mvebu-pwm",
  537. GPIO_ACTIVE_HIGH,
  538. GPIOD_OUT_LOW);
  539. if (IS_ERR(desc)) {
  540. ret = PTR_ERR(desc);
  541. goto out;
  542. }
  543. mvpwm->gpiod = desc;
  544. }
  545. out:
  546. spin_unlock_irqrestore(&mvpwm->lock, flags);
  547. return ret;
  548. }
  549. static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  550. {
  551. struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
  552. unsigned long flags;
  553. spin_lock_irqsave(&mvpwm->lock, flags);
  554. gpiochip_free_own_desc(mvpwm->gpiod);
  555. mvpwm->gpiod = NULL;
  556. spin_unlock_irqrestore(&mvpwm->lock, flags);
  557. }
  558. static int mvebu_pwm_get_state(struct pwm_chip *chip,
  559. struct pwm_device *pwm,
  560. struct pwm_state *state)
  561. {
  562. struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
  563. struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
  564. unsigned long long val;
  565. unsigned long flags;
  566. u32 u;
  567. spin_lock_irqsave(&mvpwm->lock, flags);
  568. regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
  569. /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
  570. if (u > 0)
  571. val = u;
  572. else
  573. val = UINT_MAX + 1ULL;
  574. state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
  575. mvpwm->clk_rate);
  576. regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
  577. /* period = on + off duration */
  578. if (u > 0)
  579. val += u;
  580. else
  581. val += UINT_MAX + 1ULL;
  582. state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
  583. regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
  584. if (u)
  585. state->enabled = true;
  586. else
  587. state->enabled = false;
  588. spin_unlock_irqrestore(&mvpwm->lock, flags);
  589. return 0;
  590. }
  591. static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  592. const struct pwm_state *state)
  593. {
  594. struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
  595. struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
  596. unsigned long long val;
  597. unsigned long flags;
  598. unsigned int on, off;
  599. if (state->polarity != PWM_POLARITY_NORMAL)
  600. return -EINVAL;
  601. val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
  602. do_div(val, NSEC_PER_SEC);
  603. if (val > UINT_MAX + 1ULL)
  604. return -EINVAL;
  605. /*
  606. * Zero on/off values don't work as expected. Experimentation shows
  607. * that zero value is treated as 2^32. This behavior is not documented.
  608. */
  609. if (val == UINT_MAX + 1ULL)
  610. on = 0;
  611. else if (val)
  612. on = val;
  613. else
  614. on = 1;
  615. val = (unsigned long long) mvpwm->clk_rate * state->period;
  616. do_div(val, NSEC_PER_SEC);
  617. val -= on;
  618. if (val > UINT_MAX + 1ULL)
  619. return -EINVAL;
  620. if (val == UINT_MAX + 1ULL)
  621. off = 0;
  622. else if (val)
  623. off = val;
  624. else
  625. off = 1;
  626. spin_lock_irqsave(&mvpwm->lock, flags);
  627. regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
  628. regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
  629. if (state->enabled)
  630. mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
  631. else
  632. mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
  633. spin_unlock_irqrestore(&mvpwm->lock, flags);
  634. return 0;
  635. }
  636. static const struct pwm_ops mvebu_pwm_ops = {
  637. .request = mvebu_pwm_request,
  638. .free = mvebu_pwm_free,
  639. .get_state = mvebu_pwm_get_state,
  640. .apply = mvebu_pwm_apply,
  641. .owner = THIS_MODULE,
  642. };
  643. static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
  644. {
  645. struct mvebu_pwm *mvpwm = mvchip->mvpwm;
  646. regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
  647. &mvpwm->blink_select);
  648. regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
  649. &mvpwm->blink_on_duration);
  650. regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
  651. &mvpwm->blink_off_duration);
  652. }
  653. static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
  654. {
  655. struct mvebu_pwm *mvpwm = mvchip->mvpwm;
  656. regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
  657. mvpwm->blink_select);
  658. regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
  659. mvpwm->blink_on_duration);
  660. regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
  661. mvpwm->blink_off_duration);
  662. }
  663. static int mvebu_pwm_probe(struct platform_device *pdev,
  664. struct mvebu_gpio_chip *mvchip,
  665. int id)
  666. {
  667. struct device *dev = &pdev->dev;
  668. struct mvebu_pwm *mvpwm;
  669. void __iomem *base;
  670. u32 offset;
  671. u32 set;
  672. if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
  673. int ret = of_property_read_u32(dev->of_node,
  674. "marvell,pwm-offset", &offset);
  675. if (ret < 0)
  676. return 0;
  677. } else {
  678. /*
  679. * There are only two sets of PWM configuration registers for
  680. * all the GPIO lines on those SoCs which this driver reserves
  681. * for the first two GPIO chips. So if the resource is missing
  682. * we can't treat it as an error.
  683. */
  684. if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
  685. return 0;
  686. offset = 0;
  687. }
  688. if (IS_ERR(mvchip->clk))
  689. return PTR_ERR(mvchip->clk);
  690. mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
  691. if (!mvpwm)
  692. return -ENOMEM;
  693. mvchip->mvpwm = mvpwm;
  694. mvpwm->mvchip = mvchip;
  695. mvpwm->offset = offset;
  696. if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
  697. mvpwm->regs = mvchip->regs;
  698. switch (mvchip->offset) {
  699. case AP80X_GPIO0_OFF_A8K:
  700. case CP11X_GPIO0_OFF_A8K:
  701. /* Blink counter A */
  702. set = 0;
  703. break;
  704. case CP11X_GPIO1_OFF_A8K:
  705. /* Blink counter B */
  706. set = U32_MAX;
  707. mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
  708. break;
  709. default:
  710. return -EINVAL;
  711. }
  712. } else {
  713. base = devm_platform_ioremap_resource_byname(pdev, "pwm");
  714. if (IS_ERR(base))
  715. return PTR_ERR(base);
  716. mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
  717. &mvebu_gpio_regmap_config);
  718. if (IS_ERR(mvpwm->regs))
  719. return PTR_ERR(mvpwm->regs);
  720. /*
  721. * Use set A for lines of GPIO chip with id 0, B for GPIO chip
  722. * with id 1. Don't allow further GPIO chips to be used for PWM.
  723. */
  724. if (id == 0)
  725. set = 0;
  726. else if (id == 1)
  727. set = U32_MAX;
  728. else
  729. return -EINVAL;
  730. }
  731. regmap_write(mvchip->regs,
  732. GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
  733. mvpwm->clk_rate = clk_get_rate(mvchip->clk);
  734. if (!mvpwm->clk_rate) {
  735. dev_err(dev, "failed to get clock rate\n");
  736. return -EINVAL;
  737. }
  738. mvpwm->chip.dev = dev;
  739. mvpwm->chip.ops = &mvebu_pwm_ops;
  740. mvpwm->chip.npwm = mvchip->chip.ngpio;
  741. spin_lock_init(&mvpwm->lock);
  742. return devm_pwmchip_add(dev, &mvpwm->chip);
  743. }
  744. #ifdef CONFIG_DEBUG_FS
  745. #include <linux/seq_file.h>
  746. static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  747. {
  748. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  749. u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
  750. const char *label;
  751. int i;
  752. regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
  753. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
  754. regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
  755. regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
  756. regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
  757. cause = mvebu_gpio_read_edge_cause(mvchip);
  758. edg_msk = mvebu_gpio_read_edge_mask(mvchip);
  759. lvl_msk = mvebu_gpio_read_level_mask(mvchip);
  760. for_each_requested_gpio(chip, i, label) {
  761. u32 msk;
  762. bool is_out;
  763. msk = BIT(i);
  764. is_out = !(io_conf & msk);
  765. seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
  766. if (is_out) {
  767. seq_printf(s, " out %s %s\n",
  768. out & msk ? "hi" : "lo",
  769. blink & msk ? "(blink )" : "");
  770. continue;
  771. }
  772. seq_printf(s, " in %s (act %s) - IRQ",
  773. (data_in ^ in_pol) & msk ? "hi" : "lo",
  774. in_pol & msk ? "lo" : "hi");
  775. if (!((edg_msk | lvl_msk) & msk)) {
  776. seq_puts(s, " disabled\n");
  777. continue;
  778. }
  779. if (edg_msk & msk)
  780. seq_puts(s, " edge ");
  781. if (lvl_msk & msk)
  782. seq_puts(s, " level");
  783. seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
  784. }
  785. }
  786. #else
  787. #define mvebu_gpio_dbg_show NULL
  788. #endif
  789. static const struct of_device_id mvebu_gpio_of_match[] = {
  790. {
  791. .compatible = "marvell,orion-gpio",
  792. .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
  793. },
  794. {
  795. .compatible = "marvell,mv78200-gpio",
  796. .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
  797. },
  798. {
  799. .compatible = "marvell,armadaxp-gpio",
  800. .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
  801. },
  802. {
  803. .compatible = "marvell,armada-370-gpio",
  804. .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
  805. },
  806. {
  807. .compatible = "marvell,armada-8k-gpio",
  808. .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
  809. },
  810. {
  811. /* sentinel */
  812. },
  813. };
  814. static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
  815. {
  816. struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
  817. int i;
  818. regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
  819. &mvchip->out_reg);
  820. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
  821. &mvchip->io_conf_reg);
  822. regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
  823. &mvchip->blink_en_reg);
  824. regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
  825. &mvchip->in_pol_reg);
  826. switch (mvchip->soc_variant) {
  827. case MVEBU_GPIO_SOC_VARIANT_ORION:
  828. case MVEBU_GPIO_SOC_VARIANT_A8K:
  829. regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
  830. &mvchip->edge_mask_regs[0]);
  831. regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
  832. &mvchip->level_mask_regs[0]);
  833. break;
  834. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  835. for (i = 0; i < 2; i++) {
  836. regmap_read(mvchip->regs,
  837. GPIO_EDGE_MASK_MV78200_OFF(i),
  838. &mvchip->edge_mask_regs[i]);
  839. regmap_read(mvchip->regs,
  840. GPIO_LEVEL_MASK_MV78200_OFF(i),
  841. &mvchip->level_mask_regs[i]);
  842. }
  843. break;
  844. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  845. for (i = 0; i < 4; i++) {
  846. regmap_read(mvchip->regs,
  847. GPIO_EDGE_MASK_ARMADAXP_OFF(i),
  848. &mvchip->edge_mask_regs[i]);
  849. regmap_read(mvchip->regs,
  850. GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
  851. &mvchip->level_mask_regs[i]);
  852. }
  853. break;
  854. default:
  855. BUG();
  856. }
  857. if (IS_ENABLED(CONFIG_PWM))
  858. mvebu_pwm_suspend(mvchip);
  859. return 0;
  860. }
  861. static int mvebu_gpio_resume(struct platform_device *pdev)
  862. {
  863. struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
  864. int i;
  865. regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
  866. mvchip->out_reg);
  867. regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
  868. mvchip->io_conf_reg);
  869. regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
  870. mvchip->blink_en_reg);
  871. regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
  872. mvchip->in_pol_reg);
  873. switch (mvchip->soc_variant) {
  874. case MVEBU_GPIO_SOC_VARIANT_ORION:
  875. case MVEBU_GPIO_SOC_VARIANT_A8K:
  876. regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
  877. mvchip->edge_mask_regs[0]);
  878. regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
  879. mvchip->level_mask_regs[0]);
  880. break;
  881. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  882. for (i = 0; i < 2; i++) {
  883. regmap_write(mvchip->regs,
  884. GPIO_EDGE_MASK_MV78200_OFF(i),
  885. mvchip->edge_mask_regs[i]);
  886. regmap_write(mvchip->regs,
  887. GPIO_LEVEL_MASK_MV78200_OFF(i),
  888. mvchip->level_mask_regs[i]);
  889. }
  890. break;
  891. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  892. for (i = 0; i < 4; i++) {
  893. regmap_write(mvchip->regs,
  894. GPIO_EDGE_MASK_ARMADAXP_OFF(i),
  895. mvchip->edge_mask_regs[i]);
  896. regmap_write(mvchip->regs,
  897. GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
  898. mvchip->level_mask_regs[i]);
  899. }
  900. break;
  901. default:
  902. BUG();
  903. }
  904. if (IS_ENABLED(CONFIG_PWM))
  905. mvebu_pwm_resume(mvchip);
  906. return 0;
  907. }
  908. static int mvebu_gpio_probe_raw(struct platform_device *pdev,
  909. struct mvebu_gpio_chip *mvchip)
  910. {
  911. void __iomem *base;
  912. base = devm_platform_ioremap_resource(pdev, 0);
  913. if (IS_ERR(base))
  914. return PTR_ERR(base);
  915. mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
  916. &mvebu_gpio_regmap_config);
  917. if (IS_ERR(mvchip->regs))
  918. return PTR_ERR(mvchip->regs);
  919. /*
  920. * For the legacy SoCs, the regmap directly maps to the GPIO
  921. * registers, so no offset is needed.
  922. */
  923. mvchip->offset = 0;
  924. /*
  925. * The Armada XP has a second range of registers for the
  926. * per-CPU registers
  927. */
  928. if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
  929. base = devm_platform_ioremap_resource(pdev, 1);
  930. if (IS_ERR(base))
  931. return PTR_ERR(base);
  932. mvchip->percpu_regs =
  933. devm_regmap_init_mmio(&pdev->dev, base,
  934. &mvebu_gpio_regmap_config);
  935. if (IS_ERR(mvchip->percpu_regs))
  936. return PTR_ERR(mvchip->percpu_regs);
  937. }
  938. return 0;
  939. }
  940. static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
  941. struct mvebu_gpio_chip *mvchip)
  942. {
  943. mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
  944. if (IS_ERR(mvchip->regs))
  945. return PTR_ERR(mvchip->regs);
  946. if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
  947. return -EINVAL;
  948. return 0;
  949. }
  950. static void mvebu_gpio_remove_irq_domain(void *data)
  951. {
  952. struct irq_domain *domain = data;
  953. irq_domain_remove(domain);
  954. }
  955. static int mvebu_gpio_probe(struct platform_device *pdev)
  956. {
  957. struct mvebu_gpio_chip *mvchip;
  958. const struct of_device_id *match;
  959. struct device_node *np = pdev->dev.of_node;
  960. struct irq_chip_generic *gc;
  961. struct irq_chip_type *ct;
  962. unsigned int ngpios;
  963. bool have_irqs;
  964. int soc_variant;
  965. int i, cpu, id;
  966. int err;
  967. match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
  968. if (match)
  969. soc_variant = (unsigned long) match->data;
  970. else
  971. soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
  972. /* Some gpio controllers do not provide irq support */
  973. err = platform_irq_count(pdev);
  974. if (err < 0)
  975. return err;
  976. have_irqs = err != 0;
  977. mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
  978. GFP_KERNEL);
  979. if (!mvchip)
  980. return -ENOMEM;
  981. platform_set_drvdata(pdev, mvchip);
  982. if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
  983. dev_err(&pdev->dev, "Missing ngpios OF property\n");
  984. return -ENODEV;
  985. }
  986. id = of_alias_get_id(pdev->dev.of_node, "gpio");
  987. if (id < 0) {
  988. dev_err(&pdev->dev, "Couldn't get OF id\n");
  989. return id;
  990. }
  991. mvchip->clk = devm_clk_get(&pdev->dev, NULL);
  992. /* Not all SoCs require a clock.*/
  993. if (!IS_ERR(mvchip->clk))
  994. clk_prepare_enable(mvchip->clk);
  995. mvchip->soc_variant = soc_variant;
  996. mvchip->chip.label = dev_name(&pdev->dev);
  997. mvchip->chip.parent = &pdev->dev;
  998. mvchip->chip.request = gpiochip_generic_request;
  999. mvchip->chip.free = gpiochip_generic_free;
  1000. mvchip->chip.get_direction = mvebu_gpio_get_direction;
  1001. mvchip->chip.direction_input = mvebu_gpio_direction_input;
  1002. mvchip->chip.get = mvebu_gpio_get;
  1003. mvchip->chip.direction_output = mvebu_gpio_direction_output;
  1004. mvchip->chip.set = mvebu_gpio_set;
  1005. if (have_irqs)
  1006. mvchip->chip.to_irq = mvebu_gpio_to_irq;
  1007. mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
  1008. mvchip->chip.ngpio = ngpios;
  1009. mvchip->chip.can_sleep = false;
  1010. mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
  1011. if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
  1012. err = mvebu_gpio_probe_syscon(pdev, mvchip);
  1013. else
  1014. err = mvebu_gpio_probe_raw(pdev, mvchip);
  1015. if (err)
  1016. return err;
  1017. /*
  1018. * Mask and clear GPIO interrupts.
  1019. */
  1020. switch (soc_variant) {
  1021. case MVEBU_GPIO_SOC_VARIANT_ORION:
  1022. case MVEBU_GPIO_SOC_VARIANT_A8K:
  1023. regmap_write(mvchip->regs,
  1024. GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
  1025. regmap_write(mvchip->regs,
  1026. GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
  1027. regmap_write(mvchip->regs,
  1028. GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
  1029. break;
  1030. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  1031. regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
  1032. for (cpu = 0; cpu < 2; cpu++) {
  1033. regmap_write(mvchip->regs,
  1034. GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
  1035. regmap_write(mvchip->regs,
  1036. GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
  1037. }
  1038. break;
  1039. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  1040. regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
  1041. regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
  1042. regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
  1043. for (cpu = 0; cpu < 4; cpu++) {
  1044. regmap_write(mvchip->percpu_regs,
  1045. GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
  1046. regmap_write(mvchip->percpu_regs,
  1047. GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
  1048. regmap_write(mvchip->percpu_regs,
  1049. GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
  1050. }
  1051. break;
  1052. default:
  1053. BUG();
  1054. }
  1055. devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
  1056. /* Some MVEBU SoCs have simple PWM support for GPIO lines */
  1057. if (IS_ENABLED(CONFIG_PWM)) {
  1058. err = mvebu_pwm_probe(pdev, mvchip, id);
  1059. if (err)
  1060. return err;
  1061. }
  1062. /* Some gpio controllers do not provide irq support */
  1063. if (!have_irqs)
  1064. return 0;
  1065. mvchip->domain =
  1066. irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
  1067. if (!mvchip->domain) {
  1068. dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
  1069. mvchip->chip.label);
  1070. return -ENODEV;
  1071. }
  1072. err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain,
  1073. mvchip->domain);
  1074. if (err)
  1075. return err;
  1076. err = irq_alloc_domain_generic_chips(
  1077. mvchip->domain, ngpios, 2, np->name, handle_level_irq,
  1078. IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
  1079. if (err) {
  1080. dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
  1081. mvchip->chip.label);
  1082. return err;
  1083. }
  1084. /*
  1085. * NOTE: The common accessors cannot be used because of the percpu
  1086. * access to the mask registers
  1087. */
  1088. gc = irq_get_domain_generic_chip(mvchip->domain, 0);
  1089. gc->private = mvchip;
  1090. ct = &gc->chip_types[0];
  1091. ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
  1092. ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
  1093. ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
  1094. ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
  1095. ct->chip.name = mvchip->chip.label;
  1096. ct = &gc->chip_types[1];
  1097. ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  1098. ct->chip.irq_ack = mvebu_gpio_irq_ack;
  1099. ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
  1100. ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
  1101. ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
  1102. ct->handler = handle_edge_irq;
  1103. ct->chip.name = mvchip->chip.label;
  1104. /*
  1105. * Setup the interrupt handlers. Each chip can have up to 4
  1106. * interrupt handlers, with each handler dealing with 8 GPIO
  1107. * pins.
  1108. */
  1109. for (i = 0; i < 4; i++) {
  1110. int irq = platform_get_irq_optional(pdev, i);
  1111. if (irq < 0)
  1112. continue;
  1113. irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
  1114. mvchip);
  1115. }
  1116. return 0;
  1117. }
  1118. static struct platform_driver mvebu_gpio_driver = {
  1119. .driver = {
  1120. .name = "mvebu-gpio",
  1121. .of_match_table = mvebu_gpio_of_match,
  1122. },
  1123. .probe = mvebu_gpio_probe,
  1124. .suspend = mvebu_gpio_suspend,
  1125. .resume = mvebu_gpio_resume,
  1126. };
  1127. builtin_platform_driver(mvebu_gpio_driver);