Kezdőlap Felfedezés Súgó
Bejelentkezés
samsung-sm8650
/
android_kernel_samsung_sm8650_ksu
2
0
Másolás 0
Fájlok Problémák 0 Beolvasztási kérések 0 Wiki
Fa: 8062222ad7
Branch-ok Tag-ek
android_kernel_...
/
include
/
dt-bindings
/
iio
/
qcom,spmi-adc5-gen3-pm8775.h

qcom,spmi-adc5-gen3-pm8775.h 7.6 KB
Előzmények Nyers

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146 
  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H
    7. 

  7. #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H
    8. 

  8. 

  9. #ifndef PM8775_1_SID
    10. 

  10. #define PM8775_1_SID		0
    11. 

  11. #endif
    12. 

  12. #ifndef PM8775_2_SID
    13. 

  13. #define PM8775_2_SID		2
    14. 

  14. #endif
    15. 

  15. #ifndef PM8775_3_SID
    16. 

  16. #define PM8775_3_SID		4
    17. 

  17. #endif
    18. 

  18. #ifndef PM8775_4_SID
    19. 

  19. #define PM8775_4_SID		6
    20. 

  20. #endif
    21. 

  21. 

  22. /* ADC channels for PM8775_1_ADC for PMIC5 Gen3 */
    23. 

  23. #define PM8775_1_ADC5_GEN3_OFFSET_REF			(PM8775_1_SID << 8 | 0x0)
    24. 

  24. #define PM8775_1_ADC5_GEN3_1P25VREF			(PM8775_1_SID << 8 | 0x01)
    25. 

  25. #define PM8775_1_ADC5_GEN3_VREF_VADC			(PM8775_1_SID << 8 | 0x02)
    26. 

  26. #define PM8775_1_ADC5_GEN3_DIE_TEMP			(PM8775_1_SID << 8 | 0x03)
    27. 

  27. 

  28. #define PM8775_1_ADC5_GEN3_AMUX1_THM			(PM8775_1_SID << 8 | 0x04)
    29. 

  29. #define PM8775_1_ADC5_GEN3_AMUX2_THM			(PM8775_1_SID << 8 | 0x05)
    30. 

  30. #define PM8775_1_ADC5_GEN3_AMUX3_THM			(PM8775_1_SID << 8 | 0x06)
    31. 

  31. #define PM8775_1_ADC5_GEN3_AMUX4_THM			(PM8775_1_SID << 8 | 0x07)
    32. 

  32. #define PM8775_1_ADC5_GEN3_AMUX5_THM			(PM8775_1_SID << 8 | 0x08)
    33. 

  33. #define PM8775_1_ADC5_GEN3_AMUX6_THM			(PM8775_1_SID << 8 | 0x09)
    34. 

  34. #define PM8775_1_ADC5_GEN3_AMUX1_GPIO9			(PM8775_1_SID << 8 | 0x0a)
    35. 

  35. #define PM8775_1_ADC5_GEN3_AMUX2_GPIO10			(PM8775_1_SID << 8 | 0x0b)
    36. 

  36. #define PM8775_1_ADC5_GEN3_AMUX3_GPIO11			(PM8775_1_SID << 8 | 0x0c)
    37. 

  37. #define PM8775_1_ADC5_GEN3_AMUX4_GPIO12			(PM8775_1_SID << 8 | 0x0d)
    38. 

  38. 

  39. /* 100k pull-up2 */
    40. 

  40. #define PM8775_1_ADC5_GEN3_AMUX1_THM_100K_PU		(PM8775_1_SID << 8 | 0x44)
    41. 

  41. #define PM8775_1_ADC5_GEN3_AMUX2_THM_100K_PU		(PM8775_1_SID << 8 | 0x45)
    42. 

  42. #define PM8775_1_ADC5_GEN3_AMUX3_THM_100K_PU		(PM8775_1_SID << 8 | 0x46)
    43. 

  43. #define PM8775_1_ADC5_GEN3_AMUX4_THM_100K_PU		(PM8775_1_SID << 8 | 0x47)
    44. 

  44. #define PM8775_1_ADC5_GEN3_AMUX5_THM_100K_PU		(PM8775_1_SID << 8 | 0x48)
    45. 

  45. #define PM8775_1_ADC5_GEN3_AMUX6_THM_100K_PU		(PM8775_1_SID << 8 | 0x49)
    46. 

  46. #define PM8775_1_ADC5_GEN3_AMUX1_GPIO9_100K_PU		(PM8775_1_SID << 8 | 0x4a)
    47. 

  47. #define PM8775_1_ADC5_GEN3_AMUX2_GPIO10_100K_PU		(PM8775_1_SID << 8 | 0x4b)
    48. 

  48. #define PM8775_1_ADC5_GEN3_AMUX3_GPIO11_100K_PU		(PM8775_1_SID << 8 | 0x4c)
    49. 

  49. #define PM8775_1_ADC5_GEN3_AMUX4_GPIO12_100K_PU		(PM8775_1_SID << 8 | 0x4d)
    50. 

  50. 

  51. #define PM8775_1_ADC5_GEN3_VPH_PWR			(PM8775_1_SID << 8 | 0x8e)
    52. 

  52. 

  53. /* ADC channels for PM8775_2_ADC for PMIC5 Gen3 */
    54. 

  54. #define PM8775_2_ADC5_GEN3_OFFSET_REF			(PM8775_2_SID << 8 | 0x0)
    55. 

  55. #define PM8775_2_ADC5_GEN3_1P25VREF			(PM8775_2_SID << 8 | 0x01)
    56. 

  56. #define PM8775_2_ADC5_GEN3_VREF_VADC			(PM8775_2_SID << 8 | 0x02)
    57. 

  57. #define PM8775_2_ADC5_GEN3_DIE_TEMP			(PM8775_2_SID << 8 | 0x03)
    58. 

  58. 

  59. #define PM8775_2_ADC5_GEN3_AMUX1_THM			(PM8775_2_SID << 8 | 0x04)
    60. 

  60. #define PM8775_2_ADC5_GEN3_AMUX2_THM			(PM8775_2_SID << 8 | 0x05)
    61. 

  61. #define PM8775_2_ADC5_GEN3_AMUX3_THM			(PM8775_2_SID << 8 | 0x06)
    62. 

  62. #define PM8775_2_ADC5_GEN3_AMUX4_THM			(PM8775_2_SID << 8 | 0x07)
    63. 

  63. #define PM8775_2_ADC5_GEN3_AMUX5_THM			(PM8775_2_SID << 8 | 0x08)
    64. 

  64. #define PM8775_2_ADC5_GEN3_AMUX6_THM			(PM8775_2_SID << 8 | 0x09)
    65. 

  65. #define PM8775_2_ADC5_GEN3_AMUX1_GPIO9			(PM8775_2_SID << 8 | 0x0a)
    66. 

  66. #define PM8775_2_ADC5_GEN3_AMUX2_GPIO10			(PM8775_2_SID << 8 | 0x0b)
    67. 

  67. #define PM8775_2_ADC5_GEN3_AMUX3_GPIO11			(PM8775_2_SID << 8 | 0x0c)
    68. 

  68. #define PM8775_2_ADC5_GEN3_AMUX4_GPIO12			(PM8775_2_SID << 8 | 0x0d)
    69. 

  69. 

  70. /* 100k pull-up2 */
    71. 

  71. #define PM8775_2_ADC5_GEN3_AMUX1_THM_100K_PU		(PM8775_2_SID << 8 | 0x44)
    72. 

  72. #define PM8775_2_ADC5_GEN3_AMUX2_THM_100K_PU		(PM8775_2_SID << 8 | 0x45)
    73. 

  73. #define PM8775_2_ADC5_GEN3_AMUX3_THM_100K_PU		(PM8775_2_SID << 8 | 0x46)
    74. 

  74. #define PM8775_2_ADC5_GEN3_AMUX4_THM_100K_PU		(PM8775_2_SID << 8 | 0x47)
    75. 

  75. #define PM8775_2_ADC5_GEN3_AMUX5_THM_100K_PU		(PM8775_2_SID << 8 | 0x48)
    76. 

  76. #define PM8775_2_ADC5_GEN3_AMUX6_THM_100K_PU		(PM8775_2_SID << 8 | 0x49)
    77. 

  77. #define PM8775_2_ADC5_GEN3_AMUX1_GPIO9_100K_PU		(PM8775_2_SID << 8 | 0x4a)
    78. 

  78. #define PM8775_2_ADC5_GEN3_AMUX2_GPIO10_100K_PU		(PM8775_2_SID << 8 | 0x4b)
    79. 

  79. #define PM8775_2_ADC5_GEN3_AMUX3_GPIO11_100K_PU		(PM8775_2_SID << 8 | 0x4c)
    80. 

  80. #define PM8775_2_ADC5_GEN3_AMUX4_GPIO12_100K_PU		(PM8775_2_SID << 8 | 0x4d)
    81. 

  81. 

  82. #define PM8775_2_ADC5_GEN3_VPH_PWR			(PM8775_2_SID << 8 | 0x8e)
    83. 

  83. 

  84. /* ADC channels for PM8775_3_ADC for PMIC5 Gen3 */
    85. 

  85. #define PM8775_3_ADC5_GEN3_OFFSET_REF			(PM8775_3_SID << 8 | 0x0)
    86. 

  86. #define PM8775_3_ADC5_GEN3_1P25VREF			(PM8775_3_SID << 8 | 0x01)
    87. 

  87. #define PM8775_3_ADC5_GEN3_VREF_VADC			(PM8775_3_SID << 8 | 0x02)
    88. 

  88. #define PM8775_3_ADC5_GEN3_DIE_TEMP			(PM8775_3_SID << 8 | 0x03)
    89. 

  89. 

  90. #define PM8775_3_ADC5_GEN3_AMUX1_THM			(PM8775_3_SID << 8 | 0x04)
    91. 

  91. #define PM8775_3_ADC5_GEN3_AMUX2_THM			(PM8775_3_SID << 8 | 0x05)
    92. 

  92. #define PM8775_3_ADC5_GEN3_AMUX3_THM			(PM8775_3_SID << 8 | 0x06)
    93. 

  93. #define PM8775_3_ADC5_GEN3_AMUX4_THM			(PM8775_3_SID << 8 | 0x07)
    94. 

  94. #define PM8775_3_ADC5_GEN3_AMUX5_THM			(PM8775_3_SID << 8 | 0x08)
    95. 

  95. #define PM8775_3_ADC5_GEN3_AMUX6_THM			(PM8775_3_SID << 8 | 0x09)
    96. 

  96. #define PM8775_3_ADC5_GEN3_AMUX1_GPIO9			(PM8775_3_SID << 8 | 0x0a)
    97. 

  97. #define PM8775_3_ADC5_GEN3_AMUX2_GPIO10			(PM8775_3_SID << 8 | 0x0b)
    98. 

  98. #define PM8775_3_ADC5_GEN3_AMUX3_GPIO11			(PM8775_3_SID << 8 | 0x0c)
    99. 

  99. #define PM8775_3_ADC5_GEN3_AMUX4_GPIO12			(PM8775_3_SID << 8 | 0x0d)
    100. 

  100. 

  101. /* 100k pull-up2 */
    102. 

  102. #define PM8775_3_ADC5_GEN3_AMUX1_THM_100K_PU		(PM8775_3_SID << 8 | 0x44)
    103. 

  103. #define PM8775_3_ADC5_GEN3_AMUX2_THM_100K_PU		(PM8775_3_SID << 8 | 0x45)
    104. 

  104. #define PM8775_3_ADC5_GEN3_AMUX3_THM_100K_PU		(PM8775_3_SID << 8 | 0x46)
    105. 

  105. #define PM8775_3_ADC5_GEN3_AMUX4_THM_100K_PU		(PM8775_3_SID << 8 | 0x47)
    106. 

  106. #define PM8775_3_ADC5_GEN3_AMUX5_THM_100K_PU		(PM8775_3_SID << 8 | 0x48)
    107. 

  107. #define PM8775_3_ADC5_GEN3_AMUX6_THM_100K_PU		(PM8775_3_SID << 8 | 0x49)
    108. 

  108. #define PM8775_3_ADC5_GEN3_AMUX1_GPIO9_100K_PU		(PM8775_3_SID << 8 | 0x4a)
    109. 

  109. #define PM8775_3_ADC5_GEN3_AMUX2_GPIO10_100K_PU		(PM8775_3_SID << 8 | 0x4b)
    110. 

  110. #define PM8775_3_ADC5_GEN3_AMUX3_GPIO11_100K_PU		(PM8775_3_SID << 8 | 0x4c)
    111. 

  111. #define PM8775_3_ADC5_GEN3_AMUX4_GPIO12_100K_PU		(PM8775_3_SID << 8 | 0x4d)
    112. 

  112. 

  113. #define PM8775_3_ADC5_GEN3_VPH_PWR			(PM8775_3_SID << 8 | 0x8e)
    114. 

  114. 

  115. /* ADC channels for PM8775_4_ADC for PMIC5 Gen3 */
    116. 

  116. #define PM8775_4_ADC5_GEN3_OFFSET_REF			(PM8775_4_SID << 8 | 0x0)
    117. 

  117. #define PM8775_4_ADC5_GEN3_1P25VREF			(PM8775_4_SID << 8 | 0x01)
    118. 

  118. #define PM8775_4_ADC5_GEN3_VREF_VADC			(PM8775_4_SID << 8 | 0x02)
    119. 

  119. #define PM8775_4_ADC5_GEN3_DIE_TEMP			(PM8775_4_SID << 8 | 0x03)
    120. 

  120. 

  121. #define PM8775_4_ADC5_GEN3_AMUX1_THM			(PM8775_4_SID << 8 | 0x04)
    122. 

  122. #define PM8775_4_ADC5_GEN3_AMUX2_THM			(PM8775_4_SID << 8 | 0x05)
    123. 

  123. #define PM8775_4_ADC5_GEN3_AMUX3_THM			(PM8775_4_SID << 8 | 0x06)
    124. 

  124. #define PM8775_4_ADC5_GEN3_AMUX4_THM			(PM8775_4_SID << 8 | 0x07)
    125. 

  125. #define PM8775_4_ADC5_GEN3_AMUX5_THM			(PM8775_4_SID << 8 | 0x08)
    126. 

  126. #define PM8775_4_ADC5_GEN3_AMUX6_THM			(PM8775_4_SID << 8 | 0x09)
    127. 

  127. #define PM8775_4_ADC5_GEN3_AMUX1_GPIO9			(PM8775_4_SID << 8 | 0x0a)
    128. 

  128. #define PM8775_4_ADC5_GEN3_AMUX2_GPIO10			(PM8775_4_SID << 8 | 0x0b)
    129. 

  129. #define PM8775_4_ADC5_GEN3_AMUX3_GPIO11			(PM8775_4_SID << 8 | 0x0c)
    130. 

  130. #define PM8775_4_ADC5_GEN3_AMUX4_GPIO12			(PM8775_4_SID << 8 | 0x0d)
    131. 

  131. 

  132. /* 100k pull-up2 */
    133. 

  133. #define PM8775_4_ADC5_GEN3_AMUX1_THM_100K_PU		(PM8775_4_SID << 8 | 0x44)
    134. 

  134. #define PM8775_4_ADC5_GEN3_AMUX2_THM_100K_PU		(PM8775_4_SID << 8 | 0x45)
    135. 

  135. #define PM8775_4_ADC5_GEN3_AMUX3_THM_100K_PU		(PM8775_4_SID << 8 | 0x46)
    136. 

  136. #define PM8775_4_ADC5_GEN3_AMUX4_THM_100K_PU		(PM8775_4_SID << 8 | 0x47)
    137. 

  137. #define PM8775_4_ADC5_GEN3_AMUX5_THM_100K_PU		(PM8775_4_SID << 8 | 0x48)
    138. 

  138. #define PM8775_4_ADC5_GEN3_AMUX6_THM_100K_PU		(PM8775_4_SID << 8 | 0x49)
    139. 

  139. #define PM8775_4_ADC5_GEN3_AMUX1_GPIO9_100K_PU		(PM8775_4_SID << 8 | 0x4a)
    140. 

  140. #define PM8775_4_ADC5_GEN3_AMUX2_GPIO10_100K_PU		(PM8775_4_SID << 8 | 0x4b)
    141. 

  141. #define PM8775_4_ADC5_GEN3_AMUX3_GPIO11_100K_PU		(PM8775_4_SID << 8 | 0x4c)
    142. 

  142. #define PM8775_4_ADC5_GEN3_AMUX4_GPIO12_100K_PU		(PM8775_4_SID << 8 | 0x4d)
    143. 

  143. 

  144. #define PM8775_4_ADC5_GEN3_VPH_PWR			(PM8775_4_SID << 8 | 0x8e)
    145. 

  145. 

  146. #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */
    147.