/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H #ifndef PM8775_1_SID #define PM8775_1_SID 0 #endif #ifndef PM8775_2_SID #define PM8775_2_SID 2 #endif #ifndef PM8775_3_SID #define PM8775_3_SID 4 #endif #ifndef PM8775_4_SID #define PM8775_4_SID 6 #endif /* ADC channels for PM8775_1_ADC for PMIC5 Gen3 */ #define PM8775_1_ADC5_GEN3_OFFSET_REF (PM8775_1_SID << 8 | 0x0) #define PM8775_1_ADC5_GEN3_1P25VREF (PM8775_1_SID << 8 | 0x01) #define PM8775_1_ADC5_GEN3_VREF_VADC (PM8775_1_SID << 8 | 0x02) #define PM8775_1_ADC5_GEN3_DIE_TEMP (PM8775_1_SID << 8 | 0x03) #define PM8775_1_ADC5_GEN3_AMUX1_THM (PM8775_1_SID << 8 | 0x04) #define PM8775_1_ADC5_GEN3_AMUX2_THM (PM8775_1_SID << 8 | 0x05) #define PM8775_1_ADC5_GEN3_AMUX3_THM (PM8775_1_SID << 8 | 0x06) #define PM8775_1_ADC5_GEN3_AMUX4_THM (PM8775_1_SID << 8 | 0x07) #define PM8775_1_ADC5_GEN3_AMUX5_THM (PM8775_1_SID << 8 | 0x08) #define PM8775_1_ADC5_GEN3_AMUX6_THM (PM8775_1_SID << 8 | 0x09) #define PM8775_1_ADC5_GEN3_AMUX1_GPIO9 (PM8775_1_SID << 8 | 0x0a) #define PM8775_1_ADC5_GEN3_AMUX2_GPIO10 (PM8775_1_SID << 8 | 0x0b) #define PM8775_1_ADC5_GEN3_AMUX3_GPIO11 (PM8775_1_SID << 8 | 0x0c) #define PM8775_1_ADC5_GEN3_AMUX4_GPIO12 (PM8775_1_SID << 8 | 0x0d) /* 100k pull-up2 */ #define PM8775_1_ADC5_GEN3_AMUX1_THM_100K_PU (PM8775_1_SID << 8 | 0x44) #define PM8775_1_ADC5_GEN3_AMUX2_THM_100K_PU (PM8775_1_SID << 8 | 0x45) #define PM8775_1_ADC5_GEN3_AMUX3_THM_100K_PU (PM8775_1_SID << 8 | 0x46) #define PM8775_1_ADC5_GEN3_AMUX4_THM_100K_PU (PM8775_1_SID << 8 | 0x47) #define PM8775_1_ADC5_GEN3_AMUX5_THM_100K_PU (PM8775_1_SID << 8 | 0x48) #define PM8775_1_ADC5_GEN3_AMUX6_THM_100K_PU (PM8775_1_SID << 8 | 0x49) #define PM8775_1_ADC5_GEN3_AMUX1_GPIO9_100K_PU (PM8775_1_SID << 8 | 0x4a) #define PM8775_1_ADC5_GEN3_AMUX2_GPIO10_100K_PU (PM8775_1_SID << 8 | 0x4b) #define PM8775_1_ADC5_GEN3_AMUX3_GPIO11_100K_PU (PM8775_1_SID << 8 | 0x4c) #define PM8775_1_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8775_1_SID << 8 | 0x4d) #define PM8775_1_ADC5_GEN3_VPH_PWR (PM8775_1_SID << 8 | 0x8e) /* ADC channels for PM8775_2_ADC for PMIC5 Gen3 */ #define PM8775_2_ADC5_GEN3_OFFSET_REF (PM8775_2_SID << 8 | 0x0) #define PM8775_2_ADC5_GEN3_1P25VREF (PM8775_2_SID << 8 | 0x01) #define PM8775_2_ADC5_GEN3_VREF_VADC (PM8775_2_SID << 8 | 0x02) #define PM8775_2_ADC5_GEN3_DIE_TEMP (PM8775_2_SID << 8 | 0x03) #define PM8775_2_ADC5_GEN3_AMUX1_THM (PM8775_2_SID << 8 | 0x04) #define PM8775_2_ADC5_GEN3_AMUX2_THM (PM8775_2_SID << 8 | 0x05) #define PM8775_2_ADC5_GEN3_AMUX3_THM (PM8775_2_SID << 8 | 0x06) #define PM8775_2_ADC5_GEN3_AMUX4_THM (PM8775_2_SID << 8 | 0x07) #define PM8775_2_ADC5_GEN3_AMUX5_THM (PM8775_2_SID << 8 | 0x08) #define PM8775_2_ADC5_GEN3_AMUX6_THM (PM8775_2_SID << 8 | 0x09) #define PM8775_2_ADC5_GEN3_AMUX1_GPIO9 (PM8775_2_SID << 8 | 0x0a) #define PM8775_2_ADC5_GEN3_AMUX2_GPIO10 (PM8775_2_SID << 8 | 0x0b) #define PM8775_2_ADC5_GEN3_AMUX3_GPIO11 (PM8775_2_SID << 8 | 0x0c) #define PM8775_2_ADC5_GEN3_AMUX4_GPIO12 (PM8775_2_SID << 8 | 0x0d) /* 100k pull-up2 */ #define PM8775_2_ADC5_GEN3_AMUX1_THM_100K_PU (PM8775_2_SID << 8 | 0x44) #define PM8775_2_ADC5_GEN3_AMUX2_THM_100K_PU (PM8775_2_SID << 8 | 0x45) #define PM8775_2_ADC5_GEN3_AMUX3_THM_100K_PU (PM8775_2_SID << 8 | 0x46) #define PM8775_2_ADC5_GEN3_AMUX4_THM_100K_PU (PM8775_2_SID << 8 | 0x47) #define PM8775_2_ADC5_GEN3_AMUX5_THM_100K_PU (PM8775_2_SID << 8 | 0x48) #define PM8775_2_ADC5_GEN3_AMUX6_THM_100K_PU (PM8775_2_SID << 8 | 0x49) #define PM8775_2_ADC5_GEN3_AMUX1_GPIO9_100K_PU (PM8775_2_SID << 8 | 0x4a) #define PM8775_2_ADC5_GEN3_AMUX2_GPIO10_100K_PU (PM8775_2_SID << 8 | 0x4b) #define PM8775_2_ADC5_GEN3_AMUX3_GPIO11_100K_PU (PM8775_2_SID << 8 | 0x4c) #define PM8775_2_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8775_2_SID << 8 | 0x4d) #define PM8775_2_ADC5_GEN3_VPH_PWR (PM8775_2_SID << 8 | 0x8e) /* ADC channels for PM8775_3_ADC for PMIC5 Gen3 */ #define PM8775_3_ADC5_GEN3_OFFSET_REF (PM8775_3_SID << 8 | 0x0) #define PM8775_3_ADC5_GEN3_1P25VREF (PM8775_3_SID << 8 | 0x01) #define PM8775_3_ADC5_GEN3_VREF_VADC (PM8775_3_SID << 8 | 0x02) #define PM8775_3_ADC5_GEN3_DIE_TEMP (PM8775_3_SID << 8 | 0x03) #define PM8775_3_ADC5_GEN3_AMUX1_THM (PM8775_3_SID << 8 | 0x04) #define PM8775_3_ADC5_GEN3_AMUX2_THM (PM8775_3_SID << 8 | 0x05) #define PM8775_3_ADC5_GEN3_AMUX3_THM (PM8775_3_SID << 8 | 0x06) #define PM8775_3_ADC5_GEN3_AMUX4_THM (PM8775_3_SID << 8 | 0x07) #define PM8775_3_ADC5_GEN3_AMUX5_THM (PM8775_3_SID << 8 | 0x08) #define PM8775_3_ADC5_GEN3_AMUX6_THM (PM8775_3_SID << 8 | 0x09) #define PM8775_3_ADC5_GEN3_AMUX1_GPIO9 (PM8775_3_SID << 8 | 0x0a) #define PM8775_3_ADC5_GEN3_AMUX2_GPIO10 (PM8775_3_SID << 8 | 0x0b) #define PM8775_3_ADC5_GEN3_AMUX3_GPIO11 (PM8775_3_SID << 8 | 0x0c) #define PM8775_3_ADC5_GEN3_AMUX4_GPIO12 (PM8775_3_SID << 8 | 0x0d) /* 100k pull-up2 */ #define PM8775_3_ADC5_GEN3_AMUX1_THM_100K_PU (PM8775_3_SID << 8 | 0x44) #define PM8775_3_ADC5_GEN3_AMUX2_THM_100K_PU (PM8775_3_SID << 8 | 0x45) #define PM8775_3_ADC5_GEN3_AMUX3_THM_100K_PU (PM8775_3_SID << 8 | 0x46) #define PM8775_3_ADC5_GEN3_AMUX4_THM_100K_PU (PM8775_3_SID << 8 | 0x47) #define PM8775_3_ADC5_GEN3_AMUX5_THM_100K_PU (PM8775_3_SID << 8 | 0x48) #define PM8775_3_ADC5_GEN3_AMUX6_THM_100K_PU (PM8775_3_SID << 8 | 0x49) #define PM8775_3_ADC5_GEN3_AMUX1_GPIO9_100K_PU (PM8775_3_SID << 8 | 0x4a) #define PM8775_3_ADC5_GEN3_AMUX2_GPIO10_100K_PU (PM8775_3_SID << 8 | 0x4b) #define PM8775_3_ADC5_GEN3_AMUX3_GPIO11_100K_PU (PM8775_3_SID << 8 | 0x4c) #define PM8775_3_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8775_3_SID << 8 | 0x4d) #define PM8775_3_ADC5_GEN3_VPH_PWR (PM8775_3_SID << 8 | 0x8e) /* ADC channels for PM8775_4_ADC for PMIC5 Gen3 */ #define PM8775_4_ADC5_GEN3_OFFSET_REF (PM8775_4_SID << 8 | 0x0) #define PM8775_4_ADC5_GEN3_1P25VREF (PM8775_4_SID << 8 | 0x01) #define PM8775_4_ADC5_GEN3_VREF_VADC (PM8775_4_SID << 8 | 0x02) #define PM8775_4_ADC5_GEN3_DIE_TEMP (PM8775_4_SID << 8 | 0x03) #define PM8775_4_ADC5_GEN3_AMUX1_THM (PM8775_4_SID << 8 | 0x04) #define PM8775_4_ADC5_GEN3_AMUX2_THM (PM8775_4_SID << 8 | 0x05) #define PM8775_4_ADC5_GEN3_AMUX3_THM (PM8775_4_SID << 8 | 0x06) #define PM8775_4_ADC5_GEN3_AMUX4_THM (PM8775_4_SID << 8 | 0x07) #define PM8775_4_ADC5_GEN3_AMUX5_THM (PM8775_4_SID << 8 | 0x08) #define PM8775_4_ADC5_GEN3_AMUX6_THM (PM8775_4_SID << 8 | 0x09) #define PM8775_4_ADC5_GEN3_AMUX1_GPIO9 (PM8775_4_SID << 8 | 0x0a) #define PM8775_4_ADC5_GEN3_AMUX2_GPIO10 (PM8775_4_SID << 8 | 0x0b) #define PM8775_4_ADC5_GEN3_AMUX3_GPIO11 (PM8775_4_SID << 8 | 0x0c) #define PM8775_4_ADC5_GEN3_AMUX4_GPIO12 (PM8775_4_SID << 8 | 0x0d) /* 100k pull-up2 */ #define PM8775_4_ADC5_GEN3_AMUX1_THM_100K_PU (PM8775_4_SID << 8 | 0x44) #define PM8775_4_ADC5_GEN3_AMUX2_THM_100K_PU (PM8775_4_SID << 8 | 0x45) #define PM8775_4_ADC5_GEN3_AMUX3_THM_100K_PU (PM8775_4_SID << 8 | 0x46) #define PM8775_4_ADC5_GEN3_AMUX4_THM_100K_PU (PM8775_4_SID << 8 | 0x47) #define PM8775_4_ADC5_GEN3_AMUX5_THM_100K_PU (PM8775_4_SID << 8 | 0x48) #define PM8775_4_ADC5_GEN3_AMUX6_THM_100K_PU (PM8775_4_SID << 8 | 0x49) #define PM8775_4_ADC5_GEN3_AMUX1_GPIO9_100K_PU (PM8775_4_SID << 8 | 0x4a) #define PM8775_4_ADC5_GEN3_AMUX2_GPIO10_100K_PU (PM8775_4_SID << 8 | 0x4b) #define PM8775_4_ADC5_GEN3_AMUX3_GPIO11_100K_PU (PM8775_4_SID << 8 | 0x4c) #define PM8775_4_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8775_4_SID << 8 | 0x4d) #define PM8775_4_ADC5_GEN3_VPH_PWR (PM8775_4_SID << 8 | 0x8e) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */