f853241025
UMAC HW reset feature will be using the last interrupt context in each DP interrupt combination i.e., on a system with more than 8 MSIs for DP, UMAC HW reset will be assigned a dedicated interrupt context. Add the necessary support for the same. CRs-Fixed: 3163900 Change-Id: I26abd01e4261661ed95e1aa3cb2a774e78b50d9f
97 lines
3.6 KiB
C
97 lines
3.6 KiB
C
/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _DP_UMAC_RESET_H_
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#define _DP_UMAC_RESET_H_
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#ifdef DP_UMAC_HW_RESET_SUPPORT
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#include <qdf_types.h>
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#define dp_umac_reset_alert(params...) \
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QDF_TRACE_FATAL(QDF_MODULE_ID_DP_UMAC_RESET, params)
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#define dp_umac_reset_err(params...) \
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QDF_TRACE_ERROR(QDF_MODULE_ID_DP_UMAC_RESET, params)
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#define dp_umac_reset_warn(params...) \
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QDF_TRACE_WARN(QDF_MODULE_ID_DP_UMAC_RESET, params)
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#define dp_umac_reset_notice(params...) \
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QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params)
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#define dp_umac_reset_info(params...) \
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QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params)
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#define dp_umac_reset_debug(params...) \
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QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_UMAC_RESET, params)
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#define DP_UMAC_RESET_SHMEM_ALIGN 8
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struct dp_soc;
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/**
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* enum umac_reset_state - States required for UMAC reset state machine
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* @UMAC_RESET_STATE_WAIT_FOR_PRE_RESET: Waiting for the PRE_RESET event
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* @UMAC_RESET_STATE_PRE_RESET_RECEIVED: Received the PRE_RESET event
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* @UMAC_RESET_STATE_HOST_PRE_RESET_COMPLETED: Host has completed handling the
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* PRE_RESET event
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* @UMAC_RESET_STATE_WAIT_FOR_POST_RESET: Waiting for the POST_RESET event
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* @UMAC_RESET_STATE_POST_RESET_RECEIVED: Received the POST_RESET event
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* @UMAC_RESET_STATE_HOST_POST_RESET_COMPLETED: Host has completed handling the
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* POST_RESET event
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*/
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enum umac_reset_state {
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UMAC_RESET_STATE_WAIT_FOR_PRE_RESET = 0,
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UMAC_RESET_STATE_PRE_RESET_RECEIVED,
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UMAC_RESET_STATE_HOST_PRE_RESET_COMPLETED,
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UMAC_RESET_STATE_WAIT_FOR_POST_RESET,
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UMAC_RESET_STATE_POST_RESET_RECEIVED,
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UMAC_RESET_STATE_HOST_POST_RESET_COMPLETED,
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};
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/**
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* struct umac_reset_shmem - Shared memory layout for UMAC reset feature
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* @t2h_indication: target to host communicaton
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* @h2t_indication: host to target communicaton
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*/
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struct umac_reset_shmem {
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uint32_t t2h_indication;
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uint32_t h2t_indication;
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};
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/**
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* struct dp_soc_umac_reset_ctx - UMAC reset context at soc level
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* @shmem_paddr_unaligned: Physical address of the shared memory (unaligned)
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* @shmem_vaddr_unaligned: Virtual address of the shared memory (unaligned)
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* @shmem_paddr_aligned: Physical address of the shared memory (aligned)
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* @shmem_vaddr_aligned: Virtual address of the shared memory (aligned)
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* @intr_offset: Offset of the UMAC reset interrupt w.r.t DP base interrupt
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* @current_state: current state of the UMAC reset state machine
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*/
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struct dp_soc_umac_reset_ctx {
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qdf_dma_addr_t shmem_paddr_unaligned;
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struct umac_reset_shmem *shmem_vaddr_unaligned;
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qdf_dma_addr_t shmem_paddr_aligned;
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struct umac_reset_shmem *shmem_vaddr_aligned;
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int intr_offset;
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enum umac_reset_state current_state;
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};
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/**
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* dp_soc_umac_reset_init() - Initialize UMAC reset context
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* @soc: DP soc object
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*
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* Return: QDF status of operation
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*/
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QDF_STATUS dp_soc_umac_reset_init(struct dp_soc *soc);
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#endif /* DP_UMAC_HW_RESET_SUPPORT */
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#endif /* _DP_UMAC_RESET_H_ */
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