dp_be.c 47 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  26. #include "dp_mon_2.0.h"
  27. #endif
  28. #include <hal_be_api.h>
  29. /* Generic AST entry aging timer value */
  30. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  31. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  32. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  33. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  34. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  35. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  36. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  37. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  38. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  39. };
  40. #else
  41. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  42. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  43. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  44. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  45. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  46. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  47. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  48. };
  49. #endif
  50. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  51. {
  52. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  53. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  54. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  55. /* this is used only when dmac mode is enabled */
  56. soc->num_rx_refill_buf_rings = 1;
  57. soc->wlan_cfg_ctx->notify_frame_support =
  58. DP_MARK_NOTIFY_FRAME_SUPPORT;
  59. }
  60. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  61. {
  62. switch (context_type) {
  63. case DP_CONTEXT_TYPE_SOC:
  64. return sizeof(struct dp_soc_be);
  65. case DP_CONTEXT_TYPE_PDEV:
  66. return sizeof(struct dp_pdev_be);
  67. case DP_CONTEXT_TYPE_VDEV:
  68. return sizeof(struct dp_vdev_be);
  69. case DP_CONTEXT_TYPE_PEER:
  70. return sizeof(struct dp_peer_be);
  71. default:
  72. return 0;
  73. }
  74. }
  75. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  76. qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type)
  77. {
  78. switch (context_type) {
  79. case DP_CONTEXT_TYPE_MON_SOC:
  80. return sizeof(struct dp_mon_soc_be);
  81. case DP_CONTEXT_TYPE_MON_PDEV:
  82. return sizeof(struct dp_mon_pdev_be);
  83. default:
  84. return 0;
  85. }
  86. }
  87. #else
  88. qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type)
  89. {
  90. switch (context_type) {
  91. case DP_CONTEXT_TYPE_MON_SOC:
  92. return sizeof(struct dp_mon_soc);
  93. case DP_CONTEXT_TYPE_MON_PDEV:
  94. return sizeof(struct dp_mon_pdev);
  95. default:
  96. return 0;
  97. }
  98. }
  99. #endif
  100. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  101. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  102. /**
  103. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  104. per wbm2sw ring
  105. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  106. *
  107. * Return: None
  108. */
  109. static inline
  110. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  111. {
  112. cc_cfg->wbm2sw6_cc_en = 1;
  113. cc_cfg->wbm2sw5_cc_en = 1;
  114. cc_cfg->wbm2sw4_cc_en = 1;
  115. cc_cfg->wbm2sw3_cc_en = 1;
  116. cc_cfg->wbm2sw2_cc_en = 1;
  117. /* disable wbm2sw1 hw cc as it's for FW */
  118. cc_cfg->wbm2sw1_cc_en = 0;
  119. cc_cfg->wbm2sw0_cc_en = 1;
  120. cc_cfg->wbm2fw_cc_en = 0;
  121. }
  122. #else
  123. static inline
  124. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  125. {
  126. cc_cfg->wbm2sw6_cc_en = 1;
  127. cc_cfg->wbm2sw5_cc_en = 1;
  128. cc_cfg->wbm2sw4_cc_en = 1;
  129. cc_cfg->wbm2sw3_cc_en = 1;
  130. cc_cfg->wbm2sw2_cc_en = 1;
  131. cc_cfg->wbm2sw1_cc_en = 1;
  132. cc_cfg->wbm2sw0_cc_en = 1;
  133. cc_cfg->wbm2fw_cc_en = 0;
  134. }
  135. #endif
  136. #if defined(WLAN_SUPPORT_RX_FISA)
  137. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  138. {
  139. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  140. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  141. /* get CMEM for cookie conversion */
  142. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  143. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  144. return QDF_STATUS_E_NOMEM;
  145. }
  146. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  147. soc->fst_cmem_base = soc->cmem_base +
  148. (soc->cmem_total_size - soc->cmem_avail_size);
  149. soc->cmem_avail_size -= soc->fst_cmem_size;
  150. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  151. soc->fst_cmem_base, soc->fst_cmem_size);
  152. return QDF_STATUS_SUCCESS;
  153. }
  154. #else /* !WLAN_SUPPORT_RX_FISA */
  155. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  156. {
  157. return QDF_STATUS_SUCCESS;
  158. }
  159. #endif
  160. /**
  161. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  162. conversion register
  163. * @soc: SOC handle
  164. * @is_4k_align: page address 4k alignd
  165. *
  166. * Return: None
  167. */
  168. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  169. bool is_4k_align)
  170. {
  171. struct hal_hw_cc_config cc_cfg = { 0 };
  172. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  173. if (soc->cdp_soc.ol_ops->get_con_mode &&
  174. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  175. return;
  176. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  177. dp_info("INI skip HW CC register setting");
  178. return;
  179. }
  180. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  181. cc_cfg.cc_global_en = true;
  182. cc_cfg.page_4k_align = is_4k_align;
  183. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  184. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  185. /* 36th bit should be 1 then HW know this is CMEM address */
  186. cc_cfg.lut_base_addr_39_32 = 0x10;
  187. cc_cfg.error_path_cookie_conv_en = true;
  188. cc_cfg.release_path_cookie_conv_en = true;
  189. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  190. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  191. }
  192. /**
  193. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  194. * @hal_soc_hdl: HAL SOC handle
  195. * @offset: CMEM address
  196. * @value: value to write
  197. *
  198. * Return: None.
  199. */
  200. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  201. uint32_t offset,
  202. uint32_t value)
  203. {
  204. hal_cmem_write(hal_soc_hdl, offset, value);
  205. }
  206. /**
  207. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  208. HW cookie conversion
  209. * @soc: SOC handle
  210. * @cc_ctx: cookie conversion context pointer
  211. *
  212. * Return: 0 in case of success, else error value
  213. */
  214. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  215. {
  216. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  217. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  218. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  219. /* get CMEM for cookie conversion */
  220. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  221. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  222. return QDF_STATUS_E_RESOURCES;
  223. }
  224. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  225. DP_CC_MEM_OFFSET_IN_CMEM);
  226. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  227. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  228. be_soc->cc_cmem_base, soc->cmem_avail_size);
  229. return QDF_STATUS_SUCCESS;
  230. }
  231. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  232. uint8_t for_feature)
  233. {
  234. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  235. switch (for_feature) {
  236. case COOKIE_CONVERSION:
  237. status = dp_hw_cc_cmem_addr_init(soc);
  238. break;
  239. case FISA_FST:
  240. status = dp_fisa_fst_cmem_addr_init(soc);
  241. break;
  242. default:
  243. dp_err("Invalid CMEM request");
  244. }
  245. return status;
  246. }
  247. #else
  248. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  249. bool is_4k_align) {}
  250. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  251. uint32_t offset,
  252. uint32_t value)
  253. { }
  254. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  255. {
  256. return QDF_STATUS_SUCCESS;
  257. }
  258. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  259. uint8_t for_feature)
  260. {
  261. return QDF_STATUS_SUCCESS;
  262. }
  263. #endif
  264. QDF_STATUS
  265. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  266. struct dp_hw_cookie_conversion_t *cc_ctx,
  267. uint32_t num_descs,
  268. enum dp_desc_type desc_type,
  269. uint8_t desc_pool_id)
  270. {
  271. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  272. uint32_t num_spt_pages, i = 0;
  273. struct dp_spt_page_desc *spt_desc;
  274. struct qdf_mem_dma_page_t *dma_page;
  275. uint8_t chip_id;
  276. /* estimate how many SPT DDR pages needed */
  277. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  278. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  279. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  280. dp_info("num_spt_pages needed %d", num_spt_pages);
  281. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  282. &cc_ctx->page_pool, qdf_page_size,
  283. num_spt_pages, 0, false);
  284. if (!cc_ctx->page_pool.dma_pages) {
  285. dp_err("spt ddr pages allocation failed");
  286. return QDF_STATUS_E_RESOURCES;
  287. }
  288. cc_ctx->page_desc_base = qdf_mem_malloc(
  289. num_spt_pages * sizeof(struct dp_spt_page_desc));
  290. if (!cc_ctx->page_desc_base) {
  291. dp_err("spt page descs allocation failed");
  292. goto fail_0;
  293. }
  294. chip_id = dp_mlo_get_chip_id(soc);
  295. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  296. desc_type);
  297. /* initial page desc */
  298. spt_desc = cc_ctx->page_desc_base;
  299. dma_page = cc_ctx->page_pool.dma_pages;
  300. while (i < num_spt_pages) {
  301. /* check if page address 4K aligned */
  302. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  303. dp_err("non-4k aligned pages addr %pK",
  304. (void *)dma_page[i].page_p_addr);
  305. goto fail_1;
  306. }
  307. spt_desc[i].page_v_addr =
  308. dma_page[i].page_v_addr_start;
  309. spt_desc[i].page_p_addr =
  310. dma_page[i].page_p_addr;
  311. i++;
  312. }
  313. cc_ctx->total_page_num = num_spt_pages;
  314. qdf_spinlock_create(&cc_ctx->cc_lock);
  315. return QDF_STATUS_SUCCESS;
  316. fail_1:
  317. qdf_mem_free(cc_ctx->page_desc_base);
  318. fail_0:
  319. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  320. &cc_ctx->page_pool, 0, false);
  321. return QDF_STATUS_E_FAILURE;
  322. }
  323. QDF_STATUS
  324. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  325. struct dp_hw_cookie_conversion_t *cc_ctx)
  326. {
  327. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  328. qdf_mem_free(cc_ctx->page_desc_base);
  329. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  330. &cc_ctx->page_pool, 0, false);
  331. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  332. return QDF_STATUS_SUCCESS;
  333. }
  334. QDF_STATUS
  335. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  336. struct dp_hw_cookie_conversion_t *cc_ctx)
  337. {
  338. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  339. uint32_t i = 0;
  340. struct dp_spt_page_desc *spt_desc;
  341. uint32_t ppt_index;
  342. uint32_t ppt_id_start;
  343. if (!cc_ctx->total_page_num) {
  344. dp_err("total page num is 0");
  345. return QDF_STATUS_E_INVAL;
  346. }
  347. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  348. spt_desc = cc_ctx->page_desc_base;
  349. while (i < cc_ctx->total_page_num) {
  350. /* write page PA to CMEM */
  351. dp_hw_cc_cmem_write(soc->hal_soc,
  352. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  353. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  354. (spt_desc[i].page_p_addr >>
  355. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  356. ppt_index = ppt_id_start + i;
  357. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  358. qdf_assert_always(0);
  359. spt_desc[i].ppt_index = ppt_index;
  360. be_soc->page_desc_base[ppt_index].page_v_addr =
  361. spt_desc[i].page_v_addr;
  362. i++;
  363. }
  364. return QDF_STATUS_SUCCESS;
  365. }
  366. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  367. QDF_STATUS
  368. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  369. struct dp_hw_cookie_conversion_t *cc_ctx)
  370. {
  371. uint32_t ppt_index;
  372. struct dp_spt_page_desc *spt_desc;
  373. int i = 0;
  374. spt_desc = cc_ctx->page_desc_base;
  375. while (i < cc_ctx->total_page_num) {
  376. ppt_index = spt_desc[i].ppt_index;
  377. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  378. i++;
  379. }
  380. return QDF_STATUS_SUCCESS;
  381. }
  382. #else
  383. QDF_STATUS
  384. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  385. struct dp_hw_cookie_conversion_t *cc_ctx)
  386. {
  387. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  388. uint32_t ppt_index;
  389. struct dp_spt_page_desc *spt_desc;
  390. int i = 0;
  391. spt_desc = cc_ctx->page_desc_base;
  392. while (i < cc_ctx->total_page_num) {
  393. /* reset PA in CMEM to NULL */
  394. dp_hw_cc_cmem_write(soc->hal_soc,
  395. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  396. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  397. 0);
  398. ppt_index = spt_desc[i].ppt_index;
  399. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  400. i++;
  401. }
  402. return QDF_STATUS_SUCCESS;
  403. }
  404. #endif
  405. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  406. {
  407. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  408. int i = 0;
  409. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  410. dp_hw_cookie_conversion_detach(be_soc,
  411. &be_soc->tx_cc_ctx[i]);
  412. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  413. dp_hw_cookie_conversion_detach(be_soc,
  414. &be_soc->rx_cc_ctx[i]);
  415. qdf_mem_free(be_soc->page_desc_base);
  416. be_soc->page_desc_base = NULL;
  417. return QDF_STATUS_SUCCESS;
  418. }
  419. #ifdef WLAN_MLO_MULTI_CHIP
  420. #ifdef WLAN_MCAST_MLO
  421. static inline void
  422. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  423. {
  424. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  425. be_vdev->mcast_primary = false;
  426. be_vdev->seq_num = 0;
  427. dp_tx_mcast_mlo_reinject_routing_set(soc,
  428. (void *)&be_vdev->mcast_primary);
  429. if (vdev->opmode == wlan_op_mode_ap) {
  430. if (vdev->mlo_vdev)
  431. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  432. vdev->vdev_id,
  433. HAL_TX_MCAST_CTRL_DROP);
  434. else
  435. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  436. vdev->vdev_id,
  437. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  438. }
  439. }
  440. static inline void
  441. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  442. {
  443. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  444. be_vdev->seq_num = 0;
  445. be_vdev->mcast_primary = false;
  446. vdev->mlo_vdev = false;
  447. }
  448. #else
  449. static inline void
  450. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  451. {
  452. }
  453. static inline void
  454. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  455. {
  456. }
  457. #endif
  458. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  459. {
  460. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  461. qdf_mem_set(be_vdev->partner_vdev_list,
  462. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  463. CDP_INVALID_VDEV_ID);
  464. }
  465. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  466. struct cdp_lro_hash_config *lro_hash)
  467. {
  468. dp_mlo_get_rx_hash_key(soc, lro_hash);
  469. }
  470. #else
  471. static inline void
  472. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  473. {
  474. }
  475. static inline void
  476. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  477. {
  478. }
  479. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  480. {
  481. }
  482. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  483. struct cdp_lro_hash_config *lro_hash)
  484. {
  485. dp_get_rx_hash_key_bytes(lro_hash);
  486. }
  487. #endif
  488. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  489. struct cdp_soc_attach_params *params)
  490. {
  491. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  492. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  493. uint32_t max_tx_rx_desc_num, num_spt_pages;
  494. uint32_t num_entries;
  495. int i = 0;
  496. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  497. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  498. /* estimate how many SPT DDR pages needed */
  499. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  500. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  501. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  502. be_soc->page_desc_base = qdf_mem_malloc(
  503. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  504. if (!be_soc->page_desc_base) {
  505. dp_err("spt page descs allocation failed");
  506. return QDF_STATUS_E_NOMEM;
  507. }
  508. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  509. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  510. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  511. goto fail;
  512. dp_soc_mlo_fill_params(soc, params);
  513. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  514. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  515. qdf_status =
  516. dp_hw_cookie_conversion_attach(be_soc,
  517. &be_soc->tx_cc_ctx[i],
  518. num_entries,
  519. DP_TX_DESC_TYPE, i);
  520. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  521. goto fail;
  522. }
  523. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  524. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  525. goto fail;
  526. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  527. num_entries =
  528. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  529. qdf_status =
  530. dp_hw_cookie_conversion_attach(be_soc,
  531. &be_soc->rx_cc_ctx[i],
  532. num_entries,
  533. DP_RX_DESC_BUF_TYPE, i);
  534. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  535. goto fail;
  536. }
  537. return qdf_status;
  538. fail:
  539. dp_soc_detach_be(soc);
  540. return qdf_status;
  541. }
  542. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  543. {
  544. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  545. int i = 0;
  546. dp_tx_deinit_bank_profiles(be_soc);
  547. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  548. dp_hw_cookie_conversion_deinit(be_soc,
  549. &be_soc->tx_cc_ctx[i]);
  550. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  551. dp_hw_cookie_conversion_deinit(be_soc,
  552. &be_soc->rx_cc_ctx[i]);
  553. return QDF_STATUS_SUCCESS;
  554. }
  555. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  556. {
  557. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  558. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  559. int i = 0;
  560. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  561. qdf_status =
  562. dp_hw_cookie_conversion_init(be_soc,
  563. &be_soc->tx_cc_ctx[i]);
  564. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  565. goto fail;
  566. }
  567. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  568. qdf_status =
  569. dp_hw_cookie_conversion_init(be_soc,
  570. &be_soc->rx_cc_ctx[i]);
  571. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  572. goto fail;
  573. }
  574. /* route vdev_id mismatch notification via FW completion */
  575. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  576. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  577. qdf_status = dp_tx_init_bank_profiles(be_soc);
  578. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  579. goto fail;
  580. /* write WBM/REO cookie conversion CFG register */
  581. dp_cc_reg_cfg_init(soc, true);
  582. return qdf_status;
  583. fail:
  584. dp_soc_deinit_be(soc);
  585. return qdf_status;
  586. }
  587. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  588. struct cdp_pdev_attach_params *params)
  589. {
  590. dp_pdev_mlo_fill_params(pdev, params);
  591. dp_mlo_update_link_to_pdev_map(pdev->soc, pdev);
  592. return QDF_STATUS_SUCCESS;
  593. }
  594. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  595. {
  596. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  597. return QDF_STATUS_SUCCESS;
  598. }
  599. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  600. {
  601. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  602. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  603. struct dp_pdev *pdev = vdev->pdev;
  604. if (vdev->opmode == wlan_op_mode_monitor)
  605. return QDF_STATUS_SUCCESS;
  606. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  607. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  608. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  609. QDF_BUG(0);
  610. return QDF_STATUS_E_FAULT;
  611. }
  612. if (vdev->opmode == wlan_op_mode_sta) {
  613. if (soc->cdp_soc.ol_ops->set_mec_timer)
  614. soc->cdp_soc.ol_ops->set_mec_timer(
  615. soc->ctrl_psoc,
  616. vdev->vdev_id,
  617. DP_AST_AGING_TIMER_DEFAULT_MS);
  618. if (pdev->isolation)
  619. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  620. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  621. else
  622. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  623. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  624. }
  625. dp_mlo_mcast_init(soc, vdev);
  626. dp_mlo_init_ptnr_list(vdev);
  627. return QDF_STATUS_SUCCESS;
  628. }
  629. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  630. {
  631. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  632. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  633. if (vdev->opmode == wlan_op_mode_monitor)
  634. return QDF_STATUS_SUCCESS;
  635. if (vdev->opmode == wlan_op_mode_ap)
  636. dp_mlo_mcast_deinit(soc, vdev);
  637. dp_tx_put_bank_profile(be_soc, be_vdev);
  638. dp_clr_mlo_ptnr_list(soc, vdev);
  639. return QDF_STATUS_SUCCESS;
  640. }
  641. qdf_size_t dp_get_soc_context_size_be(void)
  642. {
  643. return sizeof(struct dp_soc_be);
  644. }
  645. #ifdef NO_RX_PKT_HDR_TLV
  646. /**
  647. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  648. * @soc: Common DP soc handle
  649. *
  650. * Return: QDF_STATUS
  651. */
  652. static QDF_STATUS
  653. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  654. {
  655. int i;
  656. int mac_id;
  657. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  658. struct dp_srng *rx_mac_srng;
  659. QDF_STATUS status = QDF_STATUS_SUCCESS;
  660. /*
  661. * In Beryllium chipset msdu_start, mpdu_end
  662. * and rx_attn are part of msdu_end/mpdu_start
  663. */
  664. htt_tlv_filter.msdu_start = 0;
  665. htt_tlv_filter.mpdu_end = 0;
  666. htt_tlv_filter.attention = 0;
  667. htt_tlv_filter.mpdu_start = 1;
  668. htt_tlv_filter.msdu_end = 1;
  669. htt_tlv_filter.packet = 1;
  670. htt_tlv_filter.packet_header = 1;
  671. htt_tlv_filter.ppdu_start = 0;
  672. htt_tlv_filter.ppdu_end = 0;
  673. htt_tlv_filter.ppdu_end_user_stats = 0;
  674. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  675. htt_tlv_filter.ppdu_end_status_done = 0;
  676. htt_tlv_filter.enable_fp = 1;
  677. htt_tlv_filter.enable_md = 0;
  678. htt_tlv_filter.enable_md = 0;
  679. htt_tlv_filter.enable_mo = 0;
  680. htt_tlv_filter.fp_mgmt_filter = 0;
  681. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  682. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  683. FILTER_DATA_MCAST |
  684. FILTER_DATA_DATA);
  685. htt_tlv_filter.mo_mgmt_filter = 0;
  686. htt_tlv_filter.mo_ctrl_filter = 0;
  687. htt_tlv_filter.mo_data_filter = 0;
  688. htt_tlv_filter.md_data_filter = 0;
  689. htt_tlv_filter.offset_valid = true;
  690. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  691. htt_tlv_filter.rx_mpdu_end_offset = 0;
  692. htt_tlv_filter.rx_msdu_start_offset = 0;
  693. htt_tlv_filter.rx_attn_offset = 0;
  694. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  695. /*Not subscribing rx_pkt_header*/
  696. htt_tlv_filter.rx_header_offset = 0;
  697. htt_tlv_filter.rx_mpdu_start_offset =
  698. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  699. htt_tlv_filter.rx_msdu_end_offset =
  700. hal_rx_msdu_end_offset_get(soc->hal_soc);
  701. for (i = 0; i < MAX_PDEV_CNT; i++) {
  702. struct dp_pdev *pdev = soc->pdev_list[i];
  703. if (!pdev)
  704. continue;
  705. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  706. int mac_for_pdev =
  707. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  708. /*
  709. * Obtain lmac id from pdev to access the LMAC ring
  710. * in soc context
  711. */
  712. int lmac_id =
  713. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  714. pdev->pdev_id);
  715. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  716. if (!rx_mac_srng->hal_srng)
  717. continue;
  718. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  719. rx_mac_srng->hal_srng,
  720. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  721. &htt_tlv_filter);
  722. }
  723. }
  724. return status;
  725. }
  726. #else
  727. /**
  728. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  729. * @soc: Common DP soc handle
  730. *
  731. * Return: QDF_STATUS
  732. */
  733. static QDF_STATUS
  734. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  735. {
  736. int i;
  737. int mac_id;
  738. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  739. struct dp_srng *rx_mac_srng;
  740. QDF_STATUS status = QDF_STATUS_SUCCESS;
  741. /*
  742. * In Beryllium chipset msdu_start, mpdu_end
  743. * and rx_attn are part of msdu_end/mpdu_start
  744. */
  745. htt_tlv_filter.msdu_start = 0;
  746. htt_tlv_filter.mpdu_end = 0;
  747. htt_tlv_filter.attention = 0;
  748. htt_tlv_filter.mpdu_start = 1;
  749. htt_tlv_filter.msdu_end = 1;
  750. htt_tlv_filter.packet = 1;
  751. htt_tlv_filter.packet_header = 1;
  752. htt_tlv_filter.ppdu_start = 0;
  753. htt_tlv_filter.ppdu_end = 0;
  754. htt_tlv_filter.ppdu_end_user_stats = 0;
  755. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  756. htt_tlv_filter.ppdu_end_status_done = 0;
  757. htt_tlv_filter.enable_fp = 1;
  758. htt_tlv_filter.enable_md = 0;
  759. htt_tlv_filter.enable_md = 0;
  760. htt_tlv_filter.enable_mo = 0;
  761. htt_tlv_filter.fp_mgmt_filter = 0;
  762. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  763. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  764. FILTER_DATA_MCAST |
  765. FILTER_DATA_DATA);
  766. htt_tlv_filter.mo_mgmt_filter = 0;
  767. htt_tlv_filter.mo_ctrl_filter = 0;
  768. htt_tlv_filter.mo_data_filter = 0;
  769. htt_tlv_filter.md_data_filter = 0;
  770. htt_tlv_filter.offset_valid = true;
  771. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  772. htt_tlv_filter.rx_mpdu_end_offset = 0;
  773. htt_tlv_filter.rx_msdu_start_offset = 0;
  774. htt_tlv_filter.rx_attn_offset = 0;
  775. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  776. htt_tlv_filter.rx_header_offset =
  777. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  778. htt_tlv_filter.rx_mpdu_start_offset =
  779. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  780. htt_tlv_filter.rx_msdu_end_offset =
  781. hal_rx_msdu_end_offset_get(soc->hal_soc);
  782. dp_info("TLV subscription\n"
  783. "msdu_start %d, mpdu_end %d, attention %d"
  784. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  785. "TLV offsets\n"
  786. "msdu_start %d, mpdu_end %d, attention %d"
  787. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  788. htt_tlv_filter.msdu_start,
  789. htt_tlv_filter.mpdu_end,
  790. htt_tlv_filter.attention,
  791. htt_tlv_filter.mpdu_start,
  792. htt_tlv_filter.msdu_end,
  793. htt_tlv_filter.packet_header,
  794. htt_tlv_filter.packet,
  795. htt_tlv_filter.rx_msdu_start_offset,
  796. htt_tlv_filter.rx_mpdu_end_offset,
  797. htt_tlv_filter.rx_attn_offset,
  798. htt_tlv_filter.rx_mpdu_start_offset,
  799. htt_tlv_filter.rx_msdu_end_offset,
  800. htt_tlv_filter.rx_header_offset,
  801. htt_tlv_filter.rx_packet_offset);
  802. for (i = 0; i < MAX_PDEV_CNT; i++) {
  803. struct dp_pdev *pdev = soc->pdev_list[i];
  804. if (!pdev)
  805. continue;
  806. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  807. int mac_for_pdev =
  808. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  809. /*
  810. * Obtain lmac id from pdev to access the LMAC ring
  811. * in soc context
  812. */
  813. int lmac_id =
  814. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  815. pdev->pdev_id);
  816. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  817. if (!rx_mac_srng->hal_srng)
  818. continue;
  819. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  820. rx_mac_srng->hal_srng,
  821. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  822. &htt_tlv_filter);
  823. }
  824. }
  825. return status;
  826. }
  827. #endif
  828. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  829. /**
  830. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  831. * near-full IRQs.
  832. * @soc: Datapath SoC handle
  833. * @int_ctx: Interrupt context
  834. * @dp_budget: Budget of the work that can be done in the bottom half
  835. *
  836. * Return: work done in the handler
  837. */
  838. static uint32_t
  839. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  840. uint32_t dp_budget)
  841. {
  842. int ring = 0;
  843. int budget = dp_budget;
  844. uint32_t work_done = 0;
  845. uint32_t remaining_quota = dp_budget;
  846. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  847. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  848. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  849. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  850. int rx_near_full_mask = rx_near_full_grp_1_mask |
  851. rx_near_full_grp_2_mask;
  852. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  853. rx_near_full_mask,
  854. tx_ring_near_full_mask);
  855. if (rx_near_full_mask) {
  856. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  857. if (!(rx_near_full_mask & (1 << ring)))
  858. continue;
  859. work_done = dp_rx_nf_process(int_ctx,
  860. soc->reo_dest_ring[ring].hal_srng,
  861. ring, remaining_quota);
  862. if (work_done) {
  863. intr_stats->num_rx_ring_near_full_masks[ring]++;
  864. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  865. rx_near_full_mask, ring,
  866. work_done,
  867. budget);
  868. budget -= work_done;
  869. if (budget <= 0)
  870. goto budget_done;
  871. remaining_quota = budget;
  872. }
  873. }
  874. }
  875. if (tx_ring_near_full_mask) {
  876. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  877. if (!(tx_ring_near_full_mask & (1 << ring)))
  878. continue;
  879. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  880. soc->tx_comp_ring[ring].hal_srng,
  881. ring, remaining_quota);
  882. if (work_done) {
  883. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  884. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  885. tx_ring_near_full_mask, ring,
  886. work_done, budget);
  887. budget -= work_done;
  888. if (budget <= 0)
  889. break;
  890. remaining_quota = budget;
  891. }
  892. }
  893. }
  894. intr_stats->num_near_full_masks++;
  895. budget_done:
  896. return dp_budget - budget;
  897. }
  898. /**
  899. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  900. * state and set the reap_limit appropriately
  901. * as per the near full state
  902. * @soc: Datapath soc handle
  903. * @dp_srng: Datapath handle for SRNG
  904. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  905. * the srng near-full state
  906. *
  907. * Return: 1, if the srng is in near-full state
  908. * 0, if the srng is not in near-full state
  909. */
  910. static int
  911. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  912. struct dp_srng *dp_srng,
  913. int *max_reap_limit)
  914. {
  915. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  916. }
  917. /**
  918. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  919. * near full IRQ handling operations.
  920. * @arch_ops: arch ops handle
  921. *
  922. * Return: none
  923. */
  924. static inline void
  925. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  926. {
  927. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  928. arch_ops->dp_srng_test_and_update_nf_params =
  929. dp_srng_test_and_update_nf_params_be;
  930. }
  931. #else
  932. static inline void
  933. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  934. {
  935. }
  936. #endif
  937. #ifdef WLAN_SUPPORT_PPEDS
  938. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  939. {
  940. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  941. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  942. soc_cfg_ctx = soc->wlan_cfg_ctx;
  943. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  944. return;
  945. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  946. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  947. be_soc->ppe_release_ring.alloc_size,
  948. soc->ctrl_psoc,
  949. WLAN_MD_DP_SRNG_PPE_RELEASE,
  950. "ppe_release_ring");
  951. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  952. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  953. be_soc->ppe2tcl_ring.alloc_size,
  954. soc->ctrl_psoc,
  955. WLAN_MD_DP_SRNG_PPE2TCL,
  956. "ppe2tcl_ring");
  957. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  958. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  959. be_soc->reo2ppe_ring.alloc_size,
  960. soc->ctrl_psoc,
  961. WLAN_MD_DP_SRNG_REO2PPE,
  962. "reo2ppe_ring");
  963. }
  964. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  965. {
  966. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  967. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  968. soc_cfg_ctx = soc->wlan_cfg_ctx;
  969. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  970. return;
  971. dp_srng_free(soc, &be_soc->ppe_release_ring);
  972. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  973. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  974. }
  975. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  976. {
  977. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  978. uint32_t entries;
  979. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  980. soc_cfg_ctx = soc->wlan_cfg_ctx;
  981. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  982. return QDF_STATUS_SUCCESS;
  983. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  984. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  985. entries, 0)) {
  986. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  987. goto fail;
  988. }
  989. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  990. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  991. entries, 0)) {
  992. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  993. goto fail;
  994. }
  995. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  996. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  997. entries, 0)) {
  998. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  999. goto fail;
  1000. }
  1001. return QDF_STATUS_SUCCESS;
  1002. fail:
  1003. dp_soc_ppe_srng_free(soc);
  1004. return QDF_STATUS_E_NOMEM;
  1005. }
  1006. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1007. {
  1008. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1009. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1010. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1011. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1012. return QDF_STATUS_SUCCESS;
  1013. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  1014. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1015. goto fail;
  1016. }
  1017. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1018. be_soc->reo2ppe_ring.alloc_size,
  1019. soc->ctrl_psoc,
  1020. WLAN_MD_DP_SRNG_REO2PPE,
  1021. "reo2ppe_ring");
  1022. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  1023. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1024. goto fail;
  1025. }
  1026. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1027. be_soc->ppe2tcl_ring.alloc_size,
  1028. soc->ctrl_psoc,
  1029. WLAN_MD_DP_SRNG_PPE2TCL,
  1030. "ppe2tcl_ring");
  1031. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  1032. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  1033. goto fail;
  1034. }
  1035. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  1036. be_soc->ppe_release_ring.alloc_size,
  1037. soc->ctrl_psoc,
  1038. WLAN_MD_DP_SRNG_PPE_RELEASE,
  1039. "ppe_release_ring");
  1040. return QDF_STATUS_SUCCESS;
  1041. fail:
  1042. dp_soc_ppe_srng_deinit(soc);
  1043. return QDF_STATUS_E_NOMEM;
  1044. }
  1045. #else
  1046. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  1047. {
  1048. }
  1049. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  1050. {
  1051. }
  1052. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  1053. {
  1054. return QDF_STATUS_SUCCESS;
  1055. }
  1056. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1057. {
  1058. return QDF_STATUS_SUCCESS;
  1059. }
  1060. #endif
  1061. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1062. {
  1063. uint32_t i;
  1064. dp_soc_ppe_srng_deinit(soc);
  1065. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1066. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1067. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1068. RXDMA_BUF, 0);
  1069. }
  1070. }
  1071. }
  1072. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1073. {
  1074. uint32_t i;
  1075. dp_soc_ppe_srng_free(soc);
  1076. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1077. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1078. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1079. }
  1080. }
  1081. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1082. {
  1083. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1084. uint32_t ring_size;
  1085. uint32_t i;
  1086. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1087. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1088. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1089. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1090. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1091. RXDMA_BUF, ring_size, 0)) {
  1092. dp_err("%pK: dp_srng_alloc failed refill ring",
  1093. soc);
  1094. goto fail;
  1095. }
  1096. }
  1097. }
  1098. if (dp_soc_ppe_srng_alloc(soc)) {
  1099. dp_err("%pK: ppe rings alloc failed",
  1100. soc);
  1101. goto fail;
  1102. }
  1103. return QDF_STATUS_SUCCESS;
  1104. fail:
  1105. dp_soc_srng_free_be(soc);
  1106. return QDF_STATUS_E_NOMEM;
  1107. }
  1108. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1109. {
  1110. int i = 0;
  1111. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1112. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1113. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1114. RXDMA_BUF, 0, 0)) {
  1115. dp_err("%pK: dp_srng_init failed refill ring",
  1116. soc);
  1117. goto fail;
  1118. }
  1119. }
  1120. }
  1121. if (dp_soc_ppe_srng_init(soc)) {
  1122. dp_err("%pK: ppe rings init failed",
  1123. soc);
  1124. goto fail;
  1125. }
  1126. return QDF_STATUS_SUCCESS;
  1127. fail:
  1128. dp_soc_srng_deinit_be(soc);
  1129. return QDF_STATUS_E_NOMEM;
  1130. }
  1131. #ifdef WLAN_FEATURE_11BE_MLO
  1132. static inline unsigned
  1133. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1134. union dp_align_mac_addr *mac_addr)
  1135. {
  1136. uint32_t index;
  1137. index =
  1138. mac_addr->align2.bytes_ab ^
  1139. mac_addr->align2.bytes_cd ^
  1140. mac_addr->align2.bytes_ef;
  1141. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1142. index &= mld_hash_obj->mld_peer_hash.mask;
  1143. return index;
  1144. }
  1145. QDF_STATUS
  1146. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1147. int hash_elems)
  1148. {
  1149. int i, log2;
  1150. if (!mld_hash_obj)
  1151. return QDF_STATUS_E_FAILURE;
  1152. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1153. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1154. log2 = dp_log2_ceil(hash_elems);
  1155. hash_elems = 1 << log2;
  1156. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1157. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1158. /* allocate an array of TAILQ peer object lists */
  1159. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1160. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1161. if (!mld_hash_obj->mld_peer_hash.bins)
  1162. return QDF_STATUS_E_NOMEM;
  1163. for (i = 0; i < hash_elems; i++)
  1164. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1165. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1166. return QDF_STATUS_SUCCESS;
  1167. }
  1168. void
  1169. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1170. {
  1171. if (!mld_hash_obj)
  1172. return;
  1173. if (mld_hash_obj->mld_peer_hash.bins) {
  1174. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1175. mld_hash_obj->mld_peer_hash.bins = NULL;
  1176. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1177. }
  1178. }
  1179. #ifdef WLAN_MLO_MULTI_CHIP
  1180. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1181. {
  1182. /* In case of MULTI chip MLO peer hash table when MLO global object
  1183. * is created, avoid from SOC attach path
  1184. */
  1185. return QDF_STATUS_SUCCESS;
  1186. }
  1187. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1188. {
  1189. }
  1190. #else
  1191. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1192. {
  1193. dp_mld_peer_hash_obj_t mld_hash_obj;
  1194. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1195. if (!mld_hash_obj)
  1196. return QDF_STATUS_E_FAILURE;
  1197. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1198. }
  1199. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1200. {
  1201. dp_mld_peer_hash_obj_t mld_hash_obj;
  1202. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1203. if (!mld_hash_obj)
  1204. return;
  1205. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1206. }
  1207. #endif
  1208. static struct dp_peer *
  1209. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1210. uint8_t *peer_mac_addr,
  1211. int mac_addr_is_aligned,
  1212. enum dp_mod_id mod_id,
  1213. uint8_t vdev_id)
  1214. {
  1215. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1216. uint32_t index;
  1217. struct dp_peer *peer;
  1218. struct dp_vdev *vdev;
  1219. dp_mld_peer_hash_obj_t mld_hash_obj;
  1220. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1221. if (!mld_hash_obj)
  1222. return NULL;
  1223. if (!mld_hash_obj->mld_peer_hash.bins)
  1224. return NULL;
  1225. if (mac_addr_is_aligned) {
  1226. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1227. } else {
  1228. qdf_mem_copy(
  1229. &local_mac_addr_aligned.raw[0],
  1230. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1231. mac_addr = &local_mac_addr_aligned;
  1232. }
  1233. if (vdev_id != DP_VDEV_ALL) {
  1234. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1235. if (!vdev) {
  1236. dp_err("vdev is null\n");
  1237. return NULL;
  1238. }
  1239. } else {
  1240. vdev = NULL;
  1241. }
  1242. /* search mld peer table if no link peer for given mac address */
  1243. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1244. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1245. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1246. hash_list_elem) {
  1247. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1248. if ((vdev_id == DP_VDEV_ALL) || (
  1249. dp_peer_find_mac_addr_cmp(
  1250. &peer->vdev->mld_mac_addr,
  1251. &vdev->mld_mac_addr) == 0)) {
  1252. /* take peer reference before returning */
  1253. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1254. QDF_STATUS_SUCCESS)
  1255. peer = NULL;
  1256. if (vdev)
  1257. dp_vdev_unref_delete(soc, vdev, mod_id);
  1258. qdf_spin_unlock_bh(
  1259. &mld_hash_obj->mld_peer_hash_lock);
  1260. return peer;
  1261. }
  1262. }
  1263. }
  1264. if (vdev)
  1265. dp_vdev_unref_delete(soc, vdev, mod_id);
  1266. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1267. return NULL; /* failure */
  1268. }
  1269. static void
  1270. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1271. {
  1272. uint32_t index;
  1273. struct dp_peer *tmppeer = NULL;
  1274. int found = 0;
  1275. dp_mld_peer_hash_obj_t mld_hash_obj;
  1276. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1277. if (!mld_hash_obj)
  1278. return;
  1279. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1280. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1281. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1282. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1283. hash_list_elem) {
  1284. if (tmppeer == peer) {
  1285. found = 1;
  1286. break;
  1287. }
  1288. }
  1289. QDF_ASSERT(found);
  1290. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1291. hash_list_elem);
  1292. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1293. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1294. }
  1295. static void
  1296. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1297. {
  1298. uint32_t index;
  1299. dp_mld_peer_hash_obj_t mld_hash_obj;
  1300. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1301. if (!mld_hash_obj)
  1302. return;
  1303. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1304. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1305. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1306. DP_MOD_ID_CONFIG))) {
  1307. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1308. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1309. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1310. return;
  1311. }
  1312. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1313. hash_list_elem);
  1314. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1315. }
  1316. #endif
  1317. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1318. defined(WLAN_MCAST_MLO)
  1319. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1320. struct dp_vdev_be *be_vdev,
  1321. cdp_config_param_type val)
  1322. {
  1323. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1324. be_vdev->vdev.pdev->soc);
  1325. hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc;
  1326. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  1327. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1328. if (be_vdev->mcast_primary) {
  1329. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1330. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1331. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128,
  1332. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1333. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1334. dp_tx_mcast_mlo_reinject_routing_set,
  1335. (void *)&be_vdev->mcast_primary);
  1336. } else {
  1337. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1338. HAL_TX_MCAST_CTRL_DROP);
  1339. }
  1340. }
  1341. #else
  1342. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1343. struct dp_vdev_be *be_vdev,
  1344. cdp_config_param_type val)
  1345. {
  1346. }
  1347. #endif
  1348. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1349. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1350. uint8_t tx_ring_id,
  1351. uint8_t bm_id)
  1352. {
  1353. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1354. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1355. bm_id);
  1356. }
  1357. #else
  1358. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1359. uint8_t tx_ring_id,
  1360. uint8_t bm_id)
  1361. {
  1362. }
  1363. #endif
  1364. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1365. struct dp_vdev *vdev,
  1366. enum cdp_vdev_param_type param,
  1367. cdp_config_param_type val)
  1368. {
  1369. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1370. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1371. switch (param) {
  1372. case CDP_TX_ENCAP_TYPE:
  1373. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1374. case CDP_UPDATE_TDLS_FLAGS:
  1375. dp_tx_update_bank_profile(be_soc, be_vdev);
  1376. break;
  1377. case CDP_ENABLE_CIPHER:
  1378. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1379. dp_tx_update_bank_profile(be_soc, be_vdev);
  1380. break;
  1381. case CDP_SET_MCAST_VDEV:
  1382. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1383. break;
  1384. default:
  1385. dp_warn("invalid param %d", param);
  1386. break;
  1387. }
  1388. return QDF_STATUS_SUCCESS;
  1389. }
  1390. #ifdef WLAN_FEATURE_11BE_MLO
  1391. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1392. static inline void
  1393. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1394. {
  1395. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1396. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1397. /*
  1398. * Double the peers since we use ML indication bit
  1399. * alongwith peer_id to find peers.
  1400. */
  1401. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1402. }
  1403. #else
  1404. static inline void
  1405. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1406. {
  1407. soc->max_peer_id =
  1408. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1409. }
  1410. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1411. #else
  1412. static inline void
  1413. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1414. {
  1415. soc->max_peer_id = soc->max_peers;
  1416. }
  1417. #endif /* WLAN_FEATURE_11BE_MLO */
  1418. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1419. {
  1420. }
  1421. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1422. {
  1423. dp_soc_max_peer_id_set(soc);
  1424. return QDF_STATUS_SUCCESS;
  1425. }
  1426. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  1427. uint8_t *dest_mac,
  1428. uint8_t vdev_id)
  1429. {
  1430. struct dp_peer *peer = NULL;
  1431. peer = dp_peer_find_hash_find(soc, dest_mac, 0,
  1432. vdev_id, DP_MOD_ID_SAWF);
  1433. if (!peer) {
  1434. dp_err("Invalid peer");
  1435. return NULL;
  1436. }
  1437. return peer;
  1438. }
  1439. #ifdef WLAN_FEATURE_11BE_MLO
  1440. #ifdef WLAN_MCAST_MLO
  1441. static inline void
  1442. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1443. {
  1444. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1445. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1446. }
  1447. #else /* WLAN_MCAST_MLO */
  1448. static inline void
  1449. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1450. {
  1451. }
  1452. #endif /* WLAN_MCAST_MLO */
  1453. static inline void
  1454. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1455. {
  1456. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1457. arch_ops->mlo_peer_find_hash_detach =
  1458. dp_mlo_peer_find_hash_detach_wrapper;
  1459. arch_ops->mlo_peer_find_hash_attach =
  1460. dp_mlo_peer_find_hash_attach_wrapper;
  1461. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1462. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1463. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1464. }
  1465. #else /* WLAN_FEATURE_11BE_MLO */
  1466. static inline void
  1467. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1468. {
  1469. }
  1470. #endif /* WLAN_FEATURE_11BE_MLO */
  1471. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1472. {
  1473. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1474. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1475. arch_ops->dp_rx_process = dp_rx_process_be;
  1476. arch_ops->tx_comp_get_params_from_hal_desc =
  1477. dp_tx_comp_get_params_from_hal_desc_be;
  1478. arch_ops->dp_tx_process_htt_completion =
  1479. dp_tx_process_htt_completion_be;
  1480. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1481. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1482. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1483. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1484. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1485. dp_wbm_get_rx_desc_from_hal_desc_be;
  1486. #endif
  1487. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1488. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  1489. arch_ops->dp_rx_desc_cookie_2_va =
  1490. dp_rx_desc_cookie_2_va_be;
  1491. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  1492. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1493. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1494. arch_ops->txrx_soc_init = dp_soc_init_be;
  1495. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1496. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1497. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1498. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1499. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1500. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1501. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1502. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1503. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1504. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1505. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1506. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1507. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1508. dp_rx_peer_metadata_peer_id_get_be;
  1509. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1510. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1511. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1512. dp_initialize_arch_ops_be_mlo(arch_ops);
  1513. arch_ops->dp_peer_rx_reorder_queue_setup =
  1514. dp_peer_rx_reorder_queue_setup_be;
  1515. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1516. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  1517. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  1518. dp_init_near_full_arch_ops_be(arch_ops);
  1519. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  1520. }