- Add support to compute HW Tx completion delay on WKK
- Define arch op to calculate delay
Change-Id: I82567cc781e90fe01dc5a0edfffacd4cde73f652
CRs-Fixed: 3220911
Add delta_tqm, delta_tsf2 and mlo timestamp offset for BE.
These offsets are used to calculate hardware Tx completion delay.
delta_tsf2 and delta_tqm are updated during init. mlo timestamp
offset is updated whenever target sends the update event.
Also, adding CDP ops to set the offsets.
Change-Id: I55665982798c3a795481fa96c023bb851ea17476
CRs-Fixed: 3220906
Enable bits in WMI_INIT command to let the FW know about host's
capability to support notify frame feature. If the feature is enabled,
host can mark certain TX frames as "notify frames" for hardware and they
need not be sent to FW. FW depends on this capability exchange to decide
whether to install HW rules for frames to be sent to HW.
Change-Id: I7158e79ae0fbdc73a2f4096ae1577337e8291246
CRs-Fixed: 3209399
In case Multi chip MLO configure same hash key for
all SOCs in MLO. This change is needed to avoid
same flow traffic distributed to multiple REOs.
Change-Id: Ib6cde4ae32e58ef2d45c02d640c133458f5bfac5
CRs-Fixed: 3201978
Limit the desc pools such that the max ppt entries
do not cross limit for the hardware cookie conversion.
Change-Id: I9149b20bea0d72b466ef8c3e2ee9c0b536ffe24e
CRs-Fixed: 3201792
Add support to move FISA FST from DDR to CMEM, enable it for Kiwi
Adding CMEM support for FISA FST includes
1) Reserving CMEM memory space FISA FST
2) Add HAL macros for CMEM flow search entry
Change-Id: I45fc91a86c1ac89d3d95b246e26ea981314425a8
CRs-Fixed: 3199250
In the case of target recovery avoid accessing of HW registers
during the VAP down.
Change-Id: I4061d75ec0c153710aaa99ab7414a96136ff22f5
CRs-Fixed: 3190730
Search flag addrX and addrY will be enabled for STA + TDLS case,
but currently TX bank profile is not updated which then STA still
use default TX bank profile - index based lookup search, TX might
fail.
Update bank profile with addrX and addrY search enabled.
Change-Id: I6af12d3707b59c5d4b4bba1fc5ec05a22bfcd984
CRs-Fixed: 3148759
In WIN BE chipsets, replace the REO tid
queue programming in FW via WMI with writing to a
Host managed table shared by HW and SW. REO HW will
pick the tid queue address from the table indexed by
peer id and tid number.
Change-Id: I8107ca5116425538329b11ae3519f02b32573bac
- Fixes for compilation issues after enabling
monitor 2.0 support.
- change copyright year for all files in the chain.
Change-Id: I885e257bd8ca83850656d8a1f408c1bc34920d7a
CRs-Fixed: 3086483
For Kiwi, if force device wake mechanism is enabled for register
writing, host will try to wake up UMAC before writing real register,
this also happened for CMEM write. but during soc deinit/detach
period, device might already lose power supply and then UMAC can't
be awake from host view result in panic.
Remove HW CC CMEM cleanup which is not necessary for Kiwi as
CMEM will be re-configured during next boot up.
Change-Id: I515308c065eefbba896cb232773b8d7ffc32d385
CRs-Fixed: 3097991
As bank registers need to be reconfigured after
soc deinit. Initialize bank profiles in SOC init
instead of SOC attach
Change-Id: I3baaf62e1cb73d2882d03012e9e078523dcfe736
Multicast support for MLO
1. Following functions are newly added.
dp_rx_igmp_handler()
dp_tx_mlo_mcast_handler_be()
dp_rx_mlo_mcast_handler_be()
dp_mlo_get_mcast_primary_vdev()
Change-Id: If215f843369e6e2621ef302b924e524c86f0d30b
Use chip ID and destination peer to determine the target soc
and partner vdev for Intra-BSS in MLO case.
Change-Id: I709c52e74426c5e81b50c8063cad7669c0e7002d
In the case of RAW mode, VAP parameters encap type, dscp_to_tid map id
and cipher are not updating in bank register.
Added a API to update vdev param.
Change-Id: I702bee563e7451f403fa32292bf20680cd66e213
CRs-Fixed: 3078687
In case of WIN hal_soc will be freed in wifi down
path, this pointer is not valid at pdev_detach or
soc_detach.
Change to populate dmac source ring flag to dp_soc
as access is needed at pdev_detach or soc_detach
Change-Id: I628746bdd05ba3791d3d0e6b6dfdf160ed368e9a
Rx patch changes for multichip MLO
1. Create ini for rx ring mask for each chip
2. Configure hash based routing for each chip based
on lmac_peer_id_msb
3. Peer setup changes to configure lmac_peer_id_msb
to enable hash based routing
4. Rx Replenish changes to provide buffers back to owner
SOC of reo ring
Change-Id: Ibbe6e81f9e62d88d9bb289a082dd14b4362252c4
DP peer changes required for multi-chip MLO.
This change includes
1) Adding MLO peer to global peer hash at ML context
2) Add ML peer to all partner chips id to objtable
Change-Id: I230a6c1b14484c587b190a9a318fe9ffb1caea11
Changes needed for MLO soc attach to pass chip_id,
dp_ml_context from upper layer.
This change also takes care of assigning appropriate
RBM id for IDLE link descriptors based on chip_id.
Change-Id: I8f5f08c524d91942e6e458f048700b7bdd900107
Changes to have HW cookie conversion context per
desc pool.
This context will be used to program CMEM of the
other SOC in case multi-chip MLO.
Change-Id: I5ec68813e8fcb6d124698a52f5553acf9a7b1795
Take care of the MLO peer bit indication to be
concatenated with peer_id to access the peer map
object.
Change-Id: Ia603a728101e83829a8906d1b847f42389e78ca6
CRs-Fixed: 3039326
This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM
Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
Currently the IRQ mask for tx completion near full
interrupt is not in sync with the tx completion rings
which are enabled for WCN7850.
Fix the mask for tx completion near full interrupt.
Change-Id: I1432191b260094060873406d48e04fde5b7bc35e
CRs-Fixed: 3052650
The multicast echo check feature is moved to hardware in
Beryllium. Enable this hardware feature and also disable
the MEC handing code for Beryllium in the host.
Change-Id: I86d319963191f3ed77aba16dcccbc659906edd9f
Below are the changes in HW headers for E1.5
1) WBM2SW release source enum changed back to lithium values
2) DSCP to tid table num is added in Bank register
3) MCAST ctrl value is moved from Bank to seperate register
Change-Id: I342c451d792b1618dcb62ca9d4c77dcf4d4beeac
