dsi_display.c 204 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define MAX_TE_RECHECKS 5
  28. #define DSI_CLOCK_BITRATE_RADIX 10
  29. #define MAX_TE_SOURCE_ID 2
  30. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  31. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  32. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  33. {.boot_param = dsi_display_primary},
  34. {.boot_param = dsi_display_secondary},
  35. };
  36. static const struct of_device_id dsi_display_dt_match[] = {
  37. {.compatible = "qcom,dsi-display"},
  38. {}
  39. };
  40. bool is_skip_op_required(struct dsi_display *display)
  41. {
  42. if (!display)
  43. return false;
  44. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  45. }
  46. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  47. u32 mask, bool enable)
  48. {
  49. int i;
  50. struct dsi_display_ctrl *ctrl;
  51. if (!display)
  52. return;
  53. display_for_each_ctrl(i, display) {
  54. ctrl = &display->ctrl[i];
  55. if (!ctrl)
  56. continue;
  57. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  58. }
  59. }
  60. static int dsi_display_config_clk_gating(struct dsi_display *display,
  61. bool enable)
  62. {
  63. int rc = 0, i = 0;
  64. struct dsi_display_ctrl *mctrl, *ctrl;
  65. enum dsi_clk_gate_type clk_selection;
  66. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  67. if (!display) {
  68. DSI_ERR("Invalid params\n");
  69. return -EINVAL;
  70. }
  71. if (display->panel->host_config.force_hs_clk_lane) {
  72. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  73. return 0;
  74. }
  75. mctrl = &display->ctrl[display->clk_master_idx];
  76. if (!mctrl) {
  77. DSI_ERR("Invalid controller\n");
  78. return -EINVAL;
  79. }
  80. clk_selection = display->clk_gating_config;
  81. if (!enable) {
  82. /* for disable path, make sure to disable all clk gating */
  83. clk_selection = DSI_CLK_ALL;
  84. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  85. /* Default selection, no overrides */
  86. clk_selection = default_clk_select;
  87. } else if (clk_selection == DSI_CLK_NONE) {
  88. clk_selection = 0;
  89. }
  90. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  91. enable ? "Enabling" : "Disabling",
  92. clk_selection & BYTE_CLK ? "yes" : "no",
  93. clk_selection & PIXEL_CLK ? "yes" : "no",
  94. clk_selection & DSI_PHY ? "yes" : "no");
  95. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  96. if (rc) {
  97. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  98. display->name, enable ? "enable" : "disable",
  99. clk_selection, rc);
  100. return rc;
  101. }
  102. display_for_each_ctrl(i, display) {
  103. ctrl = &display->ctrl[i];
  104. if (!ctrl->ctrl || (ctrl == mctrl))
  105. continue;
  106. /**
  107. * In Split DSI usecase we should not enable clock gating on
  108. * DSI PHY1 to ensure no display atrifacts are seen.
  109. */
  110. clk_selection &= ~DSI_PHY;
  111. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  112. clk_selection);
  113. if (rc) {
  114. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  115. display->name, enable ? "enable" : "disable",
  116. clk_selection, rc);
  117. return rc;
  118. }
  119. }
  120. return 0;
  121. }
  122. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  123. bool enable)
  124. {
  125. int i;
  126. struct dsi_display_ctrl *ctrl;
  127. if (!display)
  128. return;
  129. display_for_each_ctrl(i, display) {
  130. ctrl = &display->ctrl[i];
  131. if (!ctrl)
  132. continue;
  133. ctrl->ctrl->esd_check_underway = enable;
  134. }
  135. }
  136. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  137. {
  138. int i;
  139. struct dsi_display_ctrl *ctrl;
  140. if (!display)
  141. return;
  142. display_for_each_ctrl(i, display) {
  143. ctrl = &display->ctrl[i];
  144. if (!ctrl)
  145. continue;
  146. dsi_ctrl_irq_update(ctrl->ctrl, en);
  147. }
  148. }
  149. void dsi_rect_intersect(const struct dsi_rect *r1,
  150. const struct dsi_rect *r2,
  151. struct dsi_rect *result)
  152. {
  153. int l, t, r, b;
  154. if (!r1 || !r2 || !result)
  155. return;
  156. l = max(r1->x, r2->x);
  157. t = max(r1->y, r2->y);
  158. r = min((r1->x + r1->w), (r2->x + r2->w));
  159. b = min((r1->y + r1->h), (r2->y + r2->h));
  160. if (r <= l || b <= t) {
  161. memset(result, 0, sizeof(*result));
  162. } else {
  163. result->x = l;
  164. result->y = t;
  165. result->w = r - l;
  166. result->h = b - t;
  167. }
  168. }
  169. int dsi_display_set_backlight(struct drm_connector *connector,
  170. void *display, u32 bl_lvl)
  171. {
  172. struct dsi_display *dsi_display = display;
  173. struct dsi_panel *panel;
  174. u32 bl_scale, bl_scale_sv;
  175. u64 bl_temp;
  176. int rc = 0;
  177. if (dsi_display == NULL || dsi_display->panel == NULL)
  178. return -EINVAL;
  179. panel = dsi_display->panel;
  180. mutex_lock(&panel->panel_lock);
  181. if (!dsi_panel_initialized(panel)) {
  182. rc = -EINVAL;
  183. goto error;
  184. }
  185. panel->bl_config.bl_level = bl_lvl;
  186. /* scale backlight */
  187. bl_scale = panel->bl_config.bl_scale;
  188. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  189. bl_scale_sv = panel->bl_config.bl_scale_sv;
  190. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  191. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  192. bl_scale, bl_scale_sv, (u32)bl_temp);
  193. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  194. DSI_CORE_CLK, DSI_CLK_ON);
  195. if (rc) {
  196. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  197. dsi_display->name, rc);
  198. goto error;
  199. }
  200. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  201. if (rc)
  202. DSI_ERR("unable to set backlight\n");
  203. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  204. DSI_CORE_CLK, DSI_CLK_OFF);
  205. if (rc) {
  206. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  207. dsi_display->name, rc);
  208. goto error;
  209. }
  210. error:
  211. mutex_unlock(&panel->panel_lock);
  212. return rc;
  213. }
  214. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  215. {
  216. int rc = 0;
  217. int i;
  218. struct dsi_display_ctrl *m_ctrl, *ctrl;
  219. bool skip_op = is_skip_op_required(display);
  220. m_ctrl = &display->ctrl[display->cmd_master_idx];
  221. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  222. if (display->cmd_engine_refcount > 0) {
  223. display->cmd_engine_refcount++;
  224. goto done;
  225. }
  226. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  227. DSI_CTRL_ENGINE_ON, skip_op);
  228. if (rc) {
  229. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  230. display->name, skip_op, rc);
  231. goto done;
  232. }
  233. display_for_each_ctrl(i, display) {
  234. ctrl = &display->ctrl[i];
  235. if (!ctrl->ctrl || (ctrl == m_ctrl))
  236. continue;
  237. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  238. DSI_CTRL_ENGINE_ON, skip_op);
  239. if (rc) {
  240. DSI_ERR(
  241. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  242. display->name, skip_op, rc);
  243. goto error_disable_master;
  244. }
  245. }
  246. display->cmd_engine_refcount++;
  247. goto done;
  248. error_disable_master:
  249. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  250. DSI_CTRL_ENGINE_OFF, skip_op);
  251. done:
  252. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  253. return rc;
  254. }
  255. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  256. {
  257. int rc = 0;
  258. int i;
  259. struct dsi_display_ctrl *m_ctrl, *ctrl;
  260. bool skip_op = is_skip_op_required(display);
  261. m_ctrl = &display->ctrl[display->cmd_master_idx];
  262. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  263. if (display->cmd_engine_refcount == 0) {
  264. DSI_ERR("[%s] Invalid refcount\n", display->name);
  265. goto done;
  266. } else if (display->cmd_engine_refcount > 1) {
  267. display->cmd_engine_refcount--;
  268. goto done;
  269. }
  270. display_for_each_ctrl(i, display) {
  271. ctrl = &display->ctrl[i];
  272. if (!ctrl->ctrl || (ctrl == m_ctrl))
  273. continue;
  274. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  275. DSI_CTRL_ENGINE_OFF, skip_op);
  276. if (rc)
  277. DSI_ERR(
  278. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  279. display->name, skip_op, rc);
  280. }
  281. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  282. DSI_CTRL_ENGINE_OFF, skip_op);
  283. if (rc) {
  284. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  285. display->name, skip_op, rc);
  286. goto error;
  287. }
  288. error:
  289. display->cmd_engine_refcount = 0;
  290. done:
  291. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  292. return rc;
  293. }
  294. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  295. {
  296. struct dsi_display *display;
  297. struct dsi_display_ctrl *display_ctrl;
  298. int rc, cnt;
  299. if (!cb_data) {
  300. DSI_ERR("aspace cb called with invalid cb_data\n");
  301. return;
  302. }
  303. display = (struct dsi_display *)cb_data;
  304. /*
  305. * acquire panel_lock to make sure no commands are in-progress
  306. * while detaching the non-secure context banks
  307. */
  308. dsi_panel_acquire_panel_lock(display->panel);
  309. if (is_detach) {
  310. /* invalidate the stored iova */
  311. display->cmd_buffer_iova = 0;
  312. /* return the virtual address mapping */
  313. msm_gem_put_vaddr(display->tx_cmd_buf);
  314. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  315. } else {
  316. rc = msm_gem_get_iova(display->tx_cmd_buf,
  317. display->aspace, &(display->cmd_buffer_iova));
  318. if (rc) {
  319. DSI_ERR("failed to get the iova rc %d\n", rc);
  320. goto end;
  321. }
  322. display->vaddr =
  323. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  324. if (IS_ERR_OR_NULL(display->vaddr)) {
  325. DSI_ERR("failed to get va rc %d\n", rc);
  326. goto end;
  327. }
  328. }
  329. display_for_each_ctrl(cnt, display) {
  330. display_ctrl = &display->ctrl[cnt];
  331. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  332. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  333. display_ctrl->ctrl->vaddr = display->vaddr;
  334. display_ctrl->ctrl->secure_mode = is_detach;
  335. }
  336. end:
  337. /* release panel_lock */
  338. dsi_panel_release_panel_lock(display->panel);
  339. }
  340. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  341. {
  342. struct dsi_display *display = (struct dsi_display *)data;
  343. /*
  344. * This irq handler is used for sole purpose of identifying
  345. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  346. * in case of display not being initialized yet
  347. */
  348. if (!display)
  349. return IRQ_HANDLED;
  350. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  351. complete_all(&display->esd_te_gate);
  352. return IRQ_HANDLED;
  353. }
  354. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  355. bool enable)
  356. {
  357. if (!display) {
  358. DSI_ERR("Invalid params\n");
  359. return;
  360. }
  361. /* Handle unbalanced irq enable/disable calls */
  362. if (enable && !display->is_te_irq_enabled) {
  363. enable_irq(gpio_to_irq(display->disp_te_gpio));
  364. display->is_te_irq_enabled = true;
  365. } else if (!enable && display->is_te_irq_enabled) {
  366. disable_irq(gpio_to_irq(display->disp_te_gpio));
  367. display->is_te_irq_enabled = false;
  368. }
  369. }
  370. static void dsi_display_register_te_irq(struct dsi_display *display)
  371. {
  372. int rc = 0;
  373. struct platform_device *pdev;
  374. struct device *dev;
  375. unsigned int te_irq;
  376. pdev = display->pdev;
  377. if (!pdev) {
  378. DSI_ERR("invalid platform device\n");
  379. return;
  380. }
  381. dev = &pdev->dev;
  382. if (!dev) {
  383. DSI_ERR("invalid device\n");
  384. return;
  385. }
  386. if (display->trusted_vm_env) {
  387. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  388. return;
  389. }
  390. if (!gpio_is_valid(display->disp_te_gpio)) {
  391. rc = -EINVAL;
  392. goto error;
  393. }
  394. init_completion(&display->esd_te_gate);
  395. te_irq = gpio_to_irq(display->disp_te_gpio);
  396. /* Avoid deferred spurious irqs with disable_irq() */
  397. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  398. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  399. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  400. "TE_GPIO", display);
  401. if (rc) {
  402. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  403. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  404. goto error;
  405. }
  406. disable_irq(te_irq);
  407. display->is_te_irq_enabled = false;
  408. return;
  409. error:
  410. /* disable the TE based ESD check */
  411. DSI_WARN("Unable to register for TE IRQ\n");
  412. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  413. display->panel->esd_config.esd_enabled = false;
  414. }
  415. /* Allocate memory for cmd dma tx buffer */
  416. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  417. {
  418. int rc = 0, cnt = 0;
  419. struct dsi_display_ctrl *display_ctrl;
  420. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  421. SZ_4K,
  422. MSM_BO_UNCACHED);
  423. if ((display->tx_cmd_buf) == NULL) {
  424. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  425. rc = -ENOMEM;
  426. goto error;
  427. }
  428. display->cmd_buffer_size = SZ_4K;
  429. display->aspace = msm_gem_smmu_address_space_get(
  430. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  431. if (PTR_ERR(display->aspace) == -ENODEV) {
  432. display->aspace = NULL;
  433. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  434. } else if (IS_ERR_OR_NULL(display->aspace)) {
  435. rc = PTR_ERR(display->aspace);
  436. display->aspace = NULL;
  437. DSI_ERR("failed to get aspace %d\n", rc);
  438. goto free_gem;
  439. } else if (display->aspace) {
  440. /* register to aspace */
  441. rc = msm_gem_address_space_register_cb(display->aspace,
  442. dsi_display_aspace_cb_locked, (void *)display);
  443. if (rc) {
  444. DSI_ERR("failed to register callback %d\n", rc);
  445. goto free_gem;
  446. }
  447. }
  448. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  449. &(display->cmd_buffer_iova));
  450. if (rc) {
  451. DSI_ERR("failed to get the iova rc %d\n", rc);
  452. goto free_aspace_cb;
  453. }
  454. display->vaddr =
  455. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  456. if (IS_ERR_OR_NULL(display->vaddr)) {
  457. DSI_ERR("failed to get va rc %d\n", rc);
  458. rc = -EINVAL;
  459. goto put_iova;
  460. }
  461. display_for_each_ctrl(cnt, display) {
  462. display_ctrl = &display->ctrl[cnt];
  463. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  464. display_ctrl->ctrl->cmd_buffer_iova =
  465. display->cmd_buffer_iova;
  466. display_ctrl->ctrl->vaddr = display->vaddr;
  467. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  468. }
  469. return rc;
  470. put_iova:
  471. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  472. free_aspace_cb:
  473. msm_gem_address_space_unregister_cb(display->aspace,
  474. dsi_display_aspace_cb_locked, display);
  475. free_gem:
  476. mutex_lock(&display->drm_dev->struct_mutex);
  477. msm_gem_free_object(display->tx_cmd_buf);
  478. mutex_unlock(&display->drm_dev->struct_mutex);
  479. error:
  480. return rc;
  481. }
  482. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  483. {
  484. int i, j = 0;
  485. int len = 0, *lenp;
  486. int group = 0, count = 0;
  487. struct drm_panel_esd_config *config;
  488. if (!panel)
  489. return false;
  490. config = &(panel->esd_config);
  491. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  492. count = config->status_cmd.count;
  493. for (i = 0; i < count; i++)
  494. len += lenp[i];
  495. for (i = 0; i < len; i++)
  496. j += len;
  497. for (j = 0; j < config->groups; ++j) {
  498. for (i = 0; i < len; ++i) {
  499. if (config->return_buf[i] !=
  500. config->status_value[group + i]) {
  501. DRM_ERROR("mismatch: 0x%x\n",
  502. config->return_buf[i]);
  503. break;
  504. }
  505. }
  506. if (i == len)
  507. return true;
  508. group += len;
  509. }
  510. return false;
  511. }
  512. static void dsi_display_parse_te_data(struct dsi_display *display)
  513. {
  514. struct platform_device *pdev;
  515. struct device *dev;
  516. int rc = 0;
  517. u32 val = 0;
  518. pdev = display->pdev;
  519. if (!pdev) {
  520. DSI_ERR("Invalid platform device\n");
  521. return;
  522. }
  523. dev = &pdev->dev;
  524. if (!dev) {
  525. DSI_ERR("Invalid platform device\n");
  526. return;
  527. }
  528. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  529. "qcom,platform-te-gpio", 0);
  530. if (display->fw)
  531. rc = dsi_parser_read_u32(display->parser_node,
  532. "qcom,panel-te-source", &val);
  533. else
  534. rc = of_property_read_u32(dev->of_node,
  535. "qcom,panel-te-source", &val);
  536. if (rc || (val > MAX_TE_SOURCE_ID)) {
  537. DSI_ERR("invalid vsync source selection\n");
  538. val = 0;
  539. }
  540. display->te_source = val;
  541. }
  542. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  543. struct dsi_panel *panel)
  544. {
  545. int i, rc = 0, count = 0, start = 0, *lenp;
  546. struct drm_panel_esd_config *config;
  547. struct dsi_cmd_desc *cmds;
  548. u32 flags = 0;
  549. if (!panel || !ctrl || !ctrl->ctrl)
  550. return -EINVAL;
  551. /*
  552. * When DSI controller is not in initialized state, we do not want to
  553. * report a false ESD failure and hence we defer until next read
  554. * happen.
  555. */
  556. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  557. return 1;
  558. config = &(panel->esd_config);
  559. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  560. count = config->status_cmd.count;
  561. cmds = config->status_cmd.cmds;
  562. flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ);
  563. if (ctrl->ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE)
  564. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  565. for (i = 0; i < count; ++i) {
  566. memset(config->status_buf, 0x0, SZ_4K);
  567. if (cmds[i].last_command) {
  568. cmds[i].msg.flags |= MIPI_DSI_MSG_LASTCOMMAND;
  569. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  570. }
  571. if ((cmds[i].msg.flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  572. (panel->panel_initialized))
  573. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  574. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  575. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  576. cmds[i].msg.rx_buf = config->status_buf;
  577. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  578. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i].msg, &flags);
  579. if (rc <= 0) {
  580. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  581. return rc;
  582. }
  583. memcpy(config->return_buf + start,
  584. config->status_buf, lenp[i]);
  585. start += lenp[i];
  586. }
  587. return rc;
  588. }
  589. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  590. struct dsi_panel *panel)
  591. {
  592. int rc = 0;
  593. rc = dsi_display_read_status(ctrl, panel);
  594. if (rc <= 0) {
  595. goto exit;
  596. } else {
  597. /*
  598. * panel status read successfully.
  599. * check for validity of the data read back.
  600. */
  601. rc = dsi_display_validate_reg_read(panel);
  602. if (!rc) {
  603. rc = -EINVAL;
  604. goto exit;
  605. }
  606. }
  607. exit:
  608. return rc;
  609. }
  610. static int dsi_display_status_reg_read(struct dsi_display *display)
  611. {
  612. int rc = 0, i;
  613. struct dsi_display_ctrl *m_ctrl, *ctrl;
  614. DSI_DEBUG(" ++\n");
  615. m_ctrl = &display->ctrl[display->cmd_master_idx];
  616. if (display->tx_cmd_buf == NULL) {
  617. rc = dsi_host_alloc_cmd_tx_buffer(display);
  618. if (rc) {
  619. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  620. goto done;
  621. }
  622. }
  623. rc = dsi_display_cmd_engine_enable(display);
  624. if (rc) {
  625. DSI_ERR("cmd engine enable failed\n");
  626. return -EPERM;
  627. }
  628. rc = dsi_display_validate_status(m_ctrl, display->panel);
  629. if (rc <= 0) {
  630. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  631. display->name, rc);
  632. goto exit;
  633. }
  634. if (!display->panel->sync_broadcast_en)
  635. goto exit;
  636. display_for_each_ctrl(i, display) {
  637. ctrl = &display->ctrl[i];
  638. if (ctrl == m_ctrl)
  639. continue;
  640. rc = dsi_display_validate_status(ctrl, display->panel);
  641. if (rc <= 0) {
  642. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  643. display->name, rc);
  644. goto exit;
  645. }
  646. }
  647. exit:
  648. dsi_display_cmd_engine_disable(display);
  649. done:
  650. return rc;
  651. }
  652. static int dsi_display_status_bta_request(struct dsi_display *display)
  653. {
  654. int rc = 0;
  655. DSI_DEBUG(" ++\n");
  656. /* TODO: trigger SW BTA and wait for acknowledgment */
  657. return rc;
  658. }
  659. static int dsi_display_status_check_te(struct dsi_display *display,
  660. int rechecks)
  661. {
  662. int rc = 1, i = 0;
  663. int const esd_te_timeout = msecs_to_jiffies(3*20);
  664. dsi_display_change_te_irq_status(display, true);
  665. for (i = 0; i < rechecks; i++) {
  666. reinit_completion(&display->esd_te_gate);
  667. if (!wait_for_completion_timeout(&display->esd_te_gate,
  668. esd_te_timeout)) {
  669. DSI_ERR("TE check failed\n");
  670. dsi_display_change_te_irq_status(display, false);
  671. return -EINVAL;
  672. }
  673. }
  674. dsi_display_change_te_irq_status(display, false);
  675. return rc;
  676. }
  677. int dsi_display_check_status(struct drm_connector *connector, void *display,
  678. bool te_check_override)
  679. {
  680. struct dsi_display *dsi_display = display;
  681. struct dsi_panel *panel;
  682. u32 status_mode;
  683. int rc = 0x1, ret;
  684. u32 mask;
  685. int te_rechecks = 1;
  686. if (!dsi_display || !dsi_display->panel)
  687. return -EINVAL;
  688. panel = dsi_display->panel;
  689. dsi_panel_acquire_panel_lock(panel);
  690. if (!panel->panel_initialized) {
  691. DSI_DEBUG("Panel not initialized\n");
  692. goto release_panel_lock;
  693. }
  694. /* Prevent another ESD check,when ESD recovery is underway */
  695. if (atomic_read(&panel->esd_recovery_pending))
  696. goto release_panel_lock;
  697. status_mode = panel->esd_config.status_mode;
  698. if (status_mode == ESD_MODE_SW_SIM_SUCCESS)
  699. goto release_panel_lock;
  700. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  701. rc = -EINVAL;
  702. goto release_panel_lock;
  703. }
  704. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  705. if (te_check_override)
  706. te_rechecks = MAX_TE_RECHECKS;
  707. ret = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  708. DSI_ALL_CLKS, DSI_CLK_ON);
  709. if (ret)
  710. goto release_panel_lock;
  711. /* Mask error interrupts before attempting ESD read */
  712. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  713. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  714. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
  715. if (status_mode == ESD_MODE_REG_READ) {
  716. rc = dsi_display_status_reg_read(dsi_display);
  717. } else if (status_mode == ESD_MODE_SW_BTA) {
  718. rc = dsi_display_status_bta_request(dsi_display);
  719. } else if (status_mode == ESD_MODE_PANEL_TE) {
  720. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  721. te_check_override = false;
  722. } else {
  723. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  724. panel->esd_config.esd_enabled = false;
  725. }
  726. if (rc <= 0 && te_check_override)
  727. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  728. /* Unmask error interrupts if check passed*/
  729. if (rc > 0) {
  730. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  731. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
  732. false);
  733. if (te_check_override && panel->esd_config.esd_enabled == false)
  734. rc = dsi_display_status_check_te(dsi_display,
  735. te_rechecks);
  736. }
  737. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  738. DSI_ALL_CLKS, DSI_CLK_OFF);
  739. /* Handle Panel failures during display disable sequence */
  740. if (rc <=0)
  741. atomic_set(&panel->esd_recovery_pending, 1);
  742. release_panel_lock:
  743. dsi_panel_release_panel_lock(panel);
  744. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  745. return rc;
  746. }
  747. static int dsi_display_cmd_prepare(const char *cmd_buf, u32 cmd_buf_len,
  748. struct dsi_cmd_desc *cmd, u8 *payload, u32 payload_len)
  749. {
  750. int i;
  751. memset(cmd, 0x00, sizeof(*cmd));
  752. cmd->msg.type = cmd_buf[0];
  753. cmd->last_command = (cmd_buf[1] == 1);
  754. cmd->msg.channel = cmd_buf[2];
  755. cmd->msg.flags = cmd_buf[3];
  756. cmd->msg.ctrl = 0;
  757. cmd->post_wait_ms = cmd->msg.wait_ms = cmd_buf[4];
  758. cmd->msg.tx_len = ((cmd_buf[5] << 8) | (cmd_buf[6]));
  759. if (cmd->msg.tx_len > payload_len) {
  760. DSI_ERR("Incorrect payload length tx_len %zu, payload_len %d\n",
  761. cmd->msg.tx_len, payload_len);
  762. return -EINVAL;
  763. }
  764. if (cmd->last_command)
  765. cmd->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND;
  766. for (i = 0; i < cmd->msg.tx_len; i++)
  767. payload[i] = cmd_buf[7 + i];
  768. cmd->msg.tx_buf = payload;
  769. return 0;
  770. }
  771. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  772. bool *state)
  773. {
  774. struct dsi_display_ctrl *ctrl;
  775. int i, rc = -EINVAL;
  776. display_for_each_ctrl(i, dsi_display) {
  777. ctrl = &dsi_display->ctrl[i];
  778. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  779. if (rc)
  780. break;
  781. }
  782. return rc;
  783. }
  784. static int dsi_display_cmd_rx(struct dsi_display *display,
  785. struct dsi_cmd_desc *cmd)
  786. {
  787. struct dsi_display_ctrl *m_ctrl = NULL;
  788. u32 mask = 0, flags = 0;
  789. int rc = 0;
  790. if (!display || !display->panel)
  791. return -EINVAL;
  792. m_ctrl = &display->ctrl[display->cmd_master_idx];
  793. if (!m_ctrl || !m_ctrl->ctrl)
  794. return -EINVAL;
  795. /* acquire panel_lock to make sure no commands are in progress */
  796. dsi_panel_acquire_panel_lock(display->panel);
  797. if (!display->panel->panel_initialized) {
  798. DSI_DEBUG("panel not initialized\n");
  799. goto release_panel_lock;
  800. }
  801. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  802. DSI_ALL_CLKS, DSI_CLK_ON);
  803. if (rc)
  804. goto release_panel_lock;
  805. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  806. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  807. rc = dsi_display_cmd_engine_enable(display);
  808. if (rc) {
  809. DSI_ERR("cmd engine enable failed rc = %d\n", rc);
  810. goto error;
  811. }
  812. flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ);
  813. if ((m_ctrl->ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) ||
  814. ((cmd->msg.flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  815. (display->panel->panel_initialized)))
  816. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  817. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmd->msg, &flags);
  818. if (rc <= 0)
  819. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  820. dsi_display_cmd_engine_disable(display);
  821. error:
  822. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  823. dsi_display_clk_ctrl(display->dsi_clk_handle,
  824. DSI_ALL_CLKS, DSI_CLK_OFF);
  825. release_panel_lock:
  826. dsi_panel_release_panel_lock(display->panel);
  827. return rc;
  828. }
  829. int dsi_display_cmd_transfer(struct drm_connector *connector,
  830. void *display, const char *cmd_buf,
  831. u32 cmd_buf_len)
  832. {
  833. struct dsi_display *dsi_display = display;
  834. struct dsi_cmd_desc cmd;
  835. u8 cmd_payload[MAX_CMD_PAYLOAD_SIZE];
  836. int rc = 0;
  837. bool state = false;
  838. if (!dsi_display || !cmd_buf) {
  839. DSI_ERR("[DSI] invalid params\n");
  840. return -EINVAL;
  841. }
  842. DSI_DEBUG("[DSI] Display command transfer\n");
  843. rc = dsi_display_cmd_prepare(cmd_buf, cmd_buf_len,
  844. &cmd, cmd_payload, MAX_CMD_PAYLOAD_SIZE);
  845. if (rc) {
  846. DSI_ERR("[DSI] command prepare failed. rc %d\n", rc);
  847. return rc;
  848. }
  849. mutex_lock(&dsi_display->display_lock);
  850. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  851. /**
  852. * Handle scenario where a command transfer is initiated through
  853. * sysfs interface when device is in suepnd state.
  854. */
  855. if (!rc && !state) {
  856. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  857. );
  858. rc = -EPERM;
  859. goto end;
  860. }
  861. if (rc || !state) {
  862. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  863. state, rc);
  864. rc = -EPERM;
  865. goto end;
  866. }
  867. rc = dsi_display->host.ops->transfer(&dsi_display->host,
  868. &cmd.msg);
  869. end:
  870. mutex_unlock(&dsi_display->display_lock);
  871. return rc;
  872. }
  873. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  874. bool enable)
  875. {
  876. int i;
  877. struct dsi_display_ctrl *ctrl;
  878. if (!display || !display->panel->host_config.force_hs_clk_lane)
  879. return;
  880. display_for_each_ctrl(i, display) {
  881. ctrl = &display->ctrl[i];
  882. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  883. }
  884. }
  885. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  886. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len)
  887. {
  888. struct dsi_display *dsi_display = display;
  889. struct dsi_cmd_desc cmd = {};
  890. u8 cmd_payload[MAX_CMD_PAYLOAD_SIZE] = {0};
  891. bool state = false;
  892. int rc = -1;
  893. if (!dsi_display || !cmd_buf || !recv_buf) {
  894. DSI_ERR("[DSI] invalid params\n");
  895. return -EINVAL;
  896. }
  897. rc = dsi_display_cmd_prepare(cmd_buf, cmd_buf_len,
  898. &cmd, cmd_payload, MAX_CMD_PAYLOAD_SIZE);
  899. if (rc) {
  900. DSI_ERR("[DSI] command prepare failed, rc = %d\n", rc);
  901. return rc;
  902. }
  903. cmd.msg.rx_buf = recv_buf;
  904. cmd.msg.rx_len = recv_buf_len;
  905. mutex_lock(&dsi_display->display_lock);
  906. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  907. if (rc || !state) {
  908. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  909. state, rc);
  910. rc = -EPERM;
  911. goto end;
  912. }
  913. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  914. if (rc <= 0)
  915. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  916. end:
  917. mutex_unlock(&dsi_display->display_lock);
  918. return rc;
  919. }
  920. int dsi_display_soft_reset(void *display)
  921. {
  922. struct dsi_display *dsi_display;
  923. struct dsi_display_ctrl *ctrl;
  924. int rc = 0;
  925. int i;
  926. if (!display)
  927. return -EINVAL;
  928. dsi_display = display;
  929. display_for_each_ctrl(i, dsi_display) {
  930. ctrl = &dsi_display->ctrl[i];
  931. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  932. if (rc) {
  933. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  934. dsi_display->name, i, rc);
  935. break;
  936. }
  937. }
  938. return rc;
  939. }
  940. enum dsi_pixel_format dsi_display_get_dst_format(
  941. struct drm_connector *connector,
  942. void *display)
  943. {
  944. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  945. struct dsi_display *dsi_display = (struct dsi_display *)display;
  946. if (!dsi_display || !dsi_display->panel) {
  947. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  948. dsi_display,
  949. ((dsi_display) ? dsi_display->panel : NULL));
  950. return format;
  951. }
  952. format = dsi_display->panel->host_config.dst_format;
  953. return format;
  954. }
  955. static void _dsi_display_setup_misr(struct dsi_display *display)
  956. {
  957. int i;
  958. display_for_each_ctrl(i, display) {
  959. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  960. display->misr_enable,
  961. display->misr_frame_count);
  962. }
  963. }
  964. int dsi_display_set_power(struct drm_connector *connector,
  965. int power_mode, void *disp)
  966. {
  967. struct dsi_display *display = disp;
  968. int rc = 0;
  969. if (!display || !display->panel) {
  970. DSI_ERR("invalid display/panel\n");
  971. return -EINVAL;
  972. }
  973. switch (power_mode) {
  974. case SDE_MODE_DPMS_LP1:
  975. rc = dsi_panel_set_lp1(display->panel);
  976. break;
  977. case SDE_MODE_DPMS_LP2:
  978. rc = dsi_panel_set_lp2(display->panel);
  979. break;
  980. case SDE_MODE_DPMS_ON:
  981. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  982. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  983. rc = dsi_panel_set_nolp(display->panel);
  984. break;
  985. case SDE_MODE_DPMS_OFF:
  986. default:
  987. return rc;
  988. }
  989. DSI_DEBUG("Power mode transition from %d to %d %s",
  990. display->panel->power_mode, power_mode,
  991. rc ? "failed" : "successful");
  992. if (!rc)
  993. display->panel->power_mode = power_mode;
  994. return rc;
  995. }
  996. #ifdef CONFIG_DEBUG_FS
  997. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  998. {
  999. u32 status_mode = 0;
  1000. if (!display->panel) {
  1001. DSI_ERR("Invalid panel data\n");
  1002. return false;
  1003. }
  1004. status_mode = display->panel->esd_config.status_mode;
  1005. if (status_mode == ESD_MODE_PANEL_TE &&
  1006. gpio_is_valid(display->disp_te_gpio))
  1007. return true;
  1008. return false;
  1009. }
  1010. static ssize_t debugfs_dump_info_read(struct file *file,
  1011. char __user *user_buf,
  1012. size_t user_len,
  1013. loff_t *ppos)
  1014. {
  1015. struct dsi_display *display = file->private_data;
  1016. char *buf;
  1017. u32 len = 0;
  1018. int i;
  1019. if (!display)
  1020. return -ENODEV;
  1021. if (*ppos)
  1022. return 0;
  1023. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1024. if (!buf)
  1025. return -ENOMEM;
  1026. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1027. len += snprintf(buf + len, (SZ_4K - len),
  1028. "\tResolution = %dx%d\n",
  1029. display->config.video_timing.h_active,
  1030. display->config.video_timing.v_active);
  1031. display_for_each_ctrl(i, display) {
  1032. len += snprintf(buf + len, (SZ_4K - len),
  1033. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1034. i, display->ctrl[i].ctrl->name,
  1035. display->ctrl[i].phy->name);
  1036. }
  1037. len += snprintf(buf + len, (SZ_4K - len),
  1038. "\tPanel = %s\n", display->panel->name);
  1039. len += snprintf(buf + len, (SZ_4K - len),
  1040. "\tClock master = %s\n",
  1041. display->ctrl[display->clk_master_idx].ctrl->name);
  1042. if (len > user_len)
  1043. len = user_len;
  1044. if (copy_to_user(user_buf, buf, len)) {
  1045. kfree(buf);
  1046. return -EFAULT;
  1047. }
  1048. *ppos += len;
  1049. kfree(buf);
  1050. return len;
  1051. }
  1052. static ssize_t debugfs_misr_setup(struct file *file,
  1053. const char __user *user_buf,
  1054. size_t user_len,
  1055. loff_t *ppos)
  1056. {
  1057. struct dsi_display *display = file->private_data;
  1058. char *buf;
  1059. int rc = 0;
  1060. size_t len;
  1061. u32 enable, frame_count;
  1062. if (!display)
  1063. return -ENODEV;
  1064. if (*ppos)
  1065. return 0;
  1066. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1067. if (!buf)
  1068. return -ENOMEM;
  1069. /* leave room for termination char */
  1070. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1071. if (copy_from_user(buf, user_buf, len)) {
  1072. rc = -EINVAL;
  1073. goto error;
  1074. }
  1075. buf[len] = '\0'; /* terminate the string */
  1076. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1077. rc = -EINVAL;
  1078. goto error;
  1079. }
  1080. display->misr_enable = enable;
  1081. display->misr_frame_count = frame_count;
  1082. mutex_lock(&display->display_lock);
  1083. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1084. DSI_CORE_CLK, DSI_CLK_ON);
  1085. if (rc) {
  1086. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1087. display->name, rc);
  1088. goto unlock;
  1089. }
  1090. _dsi_display_setup_misr(display);
  1091. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1092. DSI_CORE_CLK, DSI_CLK_OFF);
  1093. if (rc) {
  1094. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1095. display->name, rc);
  1096. goto unlock;
  1097. }
  1098. rc = user_len;
  1099. unlock:
  1100. mutex_unlock(&display->display_lock);
  1101. error:
  1102. kfree(buf);
  1103. return rc;
  1104. }
  1105. static ssize_t debugfs_misr_read(struct file *file,
  1106. char __user *user_buf,
  1107. size_t user_len,
  1108. loff_t *ppos)
  1109. {
  1110. struct dsi_display *display = file->private_data;
  1111. char *buf;
  1112. u32 len = 0;
  1113. int rc = 0;
  1114. struct dsi_ctrl *dsi_ctrl;
  1115. int i;
  1116. u32 misr;
  1117. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1118. if (!display)
  1119. return -ENODEV;
  1120. if (*ppos)
  1121. return 0;
  1122. buf = kzalloc(max_len, GFP_KERNEL);
  1123. if (ZERO_OR_NULL_PTR(buf))
  1124. return -ENOMEM;
  1125. mutex_lock(&display->display_lock);
  1126. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1127. DSI_CORE_CLK, DSI_CLK_ON);
  1128. if (rc) {
  1129. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1130. display->name, rc);
  1131. goto error;
  1132. }
  1133. display_for_each_ctrl(i, display) {
  1134. dsi_ctrl = display->ctrl[i].ctrl;
  1135. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1136. len += snprintf((buf + len), max_len - len,
  1137. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1138. if (len >= max_len)
  1139. break;
  1140. }
  1141. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1142. DSI_CORE_CLK, DSI_CLK_OFF);
  1143. if (rc) {
  1144. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1145. display->name, rc);
  1146. goto error;
  1147. }
  1148. if (copy_to_user(user_buf, buf, max_len)) {
  1149. rc = -EFAULT;
  1150. goto error;
  1151. }
  1152. *ppos += len;
  1153. error:
  1154. mutex_unlock(&display->display_lock);
  1155. kfree(buf);
  1156. return len;
  1157. }
  1158. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1159. const char __user *user_buf,
  1160. size_t user_len,
  1161. loff_t *ppos)
  1162. {
  1163. struct dsi_display *display = file->private_data;
  1164. char *buf;
  1165. int rc = 0;
  1166. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1167. u32 esd_trigger;
  1168. size_t len;
  1169. if (!display)
  1170. return -ENODEV;
  1171. if (*ppos)
  1172. return 0;
  1173. if (user_len > sizeof(u32))
  1174. return -EINVAL;
  1175. if (!user_len || !user_buf)
  1176. return -EINVAL;
  1177. if (!display->panel ||
  1178. atomic_read(&display->panel->esd_recovery_pending))
  1179. return user_len;
  1180. if (!esd_config->esd_enabled) {
  1181. DSI_ERR("ESD feature is not enabled\n");
  1182. return -EINVAL;
  1183. }
  1184. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1185. if (!buf)
  1186. return -ENOMEM;
  1187. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1188. if (copy_from_user(buf, user_buf, len)) {
  1189. rc = -EINVAL;
  1190. goto error;
  1191. }
  1192. buf[len] = '\0'; /* terminate the string */
  1193. if (kstrtouint(buf, 10, &esd_trigger)) {
  1194. rc = -EINVAL;
  1195. goto error;
  1196. }
  1197. if (esd_trigger != 1) {
  1198. rc = -EINVAL;
  1199. goto error;
  1200. }
  1201. display->esd_trigger = esd_trigger;
  1202. if (display->esd_trigger) {
  1203. DSI_INFO("ESD attack triggered by user\n");
  1204. rc = dsi_panel_trigger_esd_attack(display->panel);
  1205. if (rc) {
  1206. DSI_ERR("Failed to trigger ESD attack\n");
  1207. goto error;
  1208. }
  1209. }
  1210. rc = len;
  1211. error:
  1212. kfree(buf);
  1213. return rc;
  1214. }
  1215. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1216. const char __user *user_buf,
  1217. size_t user_len,
  1218. loff_t *ppos)
  1219. {
  1220. struct dsi_display *display = file->private_data;
  1221. struct drm_panel_esd_config *esd_config;
  1222. char *buf;
  1223. int rc = 0;
  1224. size_t len;
  1225. if (!display)
  1226. return -ENODEV;
  1227. if (*ppos)
  1228. return 0;
  1229. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1230. if (ZERO_OR_NULL_PTR(buf))
  1231. return -ENOMEM;
  1232. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1233. if (copy_from_user(buf, user_buf, len)) {
  1234. rc = -EINVAL;
  1235. goto error;
  1236. }
  1237. buf[len] = '\0'; /* terminate the string */
  1238. if (!display->panel) {
  1239. rc = -EINVAL;
  1240. goto error;
  1241. }
  1242. esd_config = &display->panel->esd_config;
  1243. if (!esd_config) {
  1244. DSI_ERR("Invalid panel esd config\n");
  1245. rc = -EINVAL;
  1246. goto error;
  1247. }
  1248. if (!esd_config->esd_enabled)
  1249. goto error;
  1250. if (!strcmp(buf, "te_signal_check\n")) {
  1251. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1252. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1253. goto error;
  1254. }
  1255. DSI_INFO("ESD check is switched to TE mode by user\n");
  1256. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1257. dsi_display_change_te_irq_status(display, true);
  1258. }
  1259. if (!strcmp(buf, "reg_read\n")) {
  1260. DSI_INFO("ESD check is switched to reg read by user\n");
  1261. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1262. if (rc) {
  1263. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1264. rc);
  1265. rc = user_len;
  1266. goto error;
  1267. }
  1268. esd_config->status_mode = ESD_MODE_REG_READ;
  1269. if (dsi_display_is_te_based_esd(display))
  1270. dsi_display_change_te_irq_status(display, false);
  1271. }
  1272. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1273. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1274. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1275. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1276. rc = len;
  1277. error:
  1278. kfree(buf);
  1279. return rc;
  1280. }
  1281. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1282. char __user *user_buf,
  1283. size_t user_len,
  1284. loff_t *ppos)
  1285. {
  1286. struct dsi_display *display = file->private_data;
  1287. struct drm_panel_esd_config *esd_config;
  1288. char *buf;
  1289. int rc = 0;
  1290. size_t len = 0;
  1291. if (!display)
  1292. return -ENODEV;
  1293. if (*ppos)
  1294. return 0;
  1295. if (!display->panel) {
  1296. DSI_ERR("invalid panel data\n");
  1297. return -EINVAL;
  1298. }
  1299. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1300. if (ZERO_OR_NULL_PTR(buf))
  1301. return -ENOMEM;
  1302. esd_config = &display->panel->esd_config;
  1303. if (!esd_config) {
  1304. DSI_ERR("Invalid panel esd config\n");
  1305. rc = -EINVAL;
  1306. goto error;
  1307. }
  1308. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1309. if (!esd_config->esd_enabled) {
  1310. rc = snprintf(buf, len, "ESD feature not enabled");
  1311. goto output_mode;
  1312. }
  1313. switch (esd_config->status_mode) {
  1314. case ESD_MODE_REG_READ:
  1315. rc = snprintf(buf, len, "reg_read");
  1316. break;
  1317. case ESD_MODE_PANEL_TE:
  1318. rc = snprintf(buf, len, "te_signal_check");
  1319. break;
  1320. case ESD_MODE_SW_SIM_FAILURE:
  1321. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1322. break;
  1323. case ESD_MODE_SW_SIM_SUCCESS:
  1324. rc = snprintf(buf, len, "esd_sw_sim_success");
  1325. break;
  1326. default:
  1327. rc = snprintf(buf, len, "invalid");
  1328. break;
  1329. }
  1330. output_mode:
  1331. if (!rc) {
  1332. rc = -EINVAL;
  1333. goto error;
  1334. }
  1335. if (copy_to_user(user_buf, buf, len)) {
  1336. rc = -EFAULT;
  1337. goto error;
  1338. }
  1339. *ppos += len;
  1340. error:
  1341. kfree(buf);
  1342. return len;
  1343. }
  1344. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1345. const char __user *user_buf,
  1346. size_t user_len,
  1347. loff_t *ppos)
  1348. {
  1349. struct dsi_display *display = file->private_data;
  1350. struct dsi_display_ctrl *display_ctrl;
  1351. char *buf;
  1352. int rc = 0;
  1353. u32 line = 0, window = 0;
  1354. size_t len;
  1355. int i;
  1356. if (!display)
  1357. return -ENODEV;
  1358. if (*ppos)
  1359. return 0;
  1360. buf = kzalloc(256, GFP_KERNEL);
  1361. if (ZERO_OR_NULL_PTR(buf))
  1362. return -ENOMEM;
  1363. len = min_t(size_t, user_len, 255);
  1364. if (copy_from_user(buf, user_buf, len)) {
  1365. rc = -EINVAL;
  1366. goto error;
  1367. }
  1368. buf[len] = '\0'; /* terminate the string */
  1369. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1370. return -EFAULT;
  1371. display_for_each_ctrl(i, display) {
  1372. struct dsi_ctrl *ctrl;
  1373. display_ctrl = &display->ctrl[i];
  1374. if (!display_ctrl->ctrl)
  1375. continue;
  1376. ctrl = display_ctrl->ctrl;
  1377. ctrl->host_config.common_config.dma_sched_line = line;
  1378. ctrl->host_config.common_config.dma_sched_window = window;
  1379. }
  1380. rc = len;
  1381. error:
  1382. kfree(buf);
  1383. return rc;
  1384. }
  1385. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1386. char __user *user_buf,
  1387. size_t user_len,
  1388. loff_t *ppos)
  1389. {
  1390. struct dsi_display *display = file->private_data;
  1391. struct dsi_display_ctrl *m_ctrl;
  1392. struct dsi_ctrl *ctrl;
  1393. char *buf;
  1394. u32 len = 0;
  1395. int rc = 0;
  1396. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1397. if (!display)
  1398. return -ENODEV;
  1399. if (*ppos)
  1400. return 0;
  1401. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1402. ctrl = m_ctrl->ctrl;
  1403. buf = kzalloc(max_len, GFP_KERNEL);
  1404. if (ZERO_OR_NULL_PTR(buf))
  1405. return -ENOMEM;
  1406. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1407. ctrl->host_config.common_config.dma_sched_line);
  1408. len += scnprintf((buf + len), max_len - len,
  1409. "Schedule command window width: %d\n",
  1410. ctrl->host_config.common_config.dma_sched_window);
  1411. if (len > max_len)
  1412. len = max_len;
  1413. if (copy_to_user(user_buf, buf, len)) {
  1414. rc = -EFAULT;
  1415. goto error;
  1416. }
  1417. *ppos += len;
  1418. error:
  1419. kfree(buf);
  1420. return len;
  1421. }
  1422. static const struct file_operations dump_info_fops = {
  1423. .open = simple_open,
  1424. .read = debugfs_dump_info_read,
  1425. };
  1426. static const struct file_operations misr_data_fops = {
  1427. .open = simple_open,
  1428. .read = debugfs_misr_read,
  1429. .write = debugfs_misr_setup,
  1430. };
  1431. static const struct file_operations esd_trigger_fops = {
  1432. .open = simple_open,
  1433. .write = debugfs_esd_trigger_check,
  1434. };
  1435. static const struct file_operations esd_check_mode_fops = {
  1436. .open = simple_open,
  1437. .write = debugfs_alter_esd_check_mode,
  1438. .read = debugfs_read_esd_check_mode,
  1439. };
  1440. static const struct file_operations dsi_command_scheduling_fops = {
  1441. .open = simple_open,
  1442. .write = debugfs_update_cmd_scheduling_params,
  1443. .read = debugfs_read_cmd_scheduling_params,
  1444. };
  1445. static int dsi_display_debugfs_init(struct dsi_display *display)
  1446. {
  1447. int rc = 0;
  1448. struct dentry *dir, *dump_file, *misr_data;
  1449. char name[MAX_NAME_SIZE];
  1450. int i;
  1451. dir = debugfs_create_dir(display->name, NULL);
  1452. if (IS_ERR_OR_NULL(dir)) {
  1453. rc = PTR_ERR(dir);
  1454. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1455. display->name, rc);
  1456. goto error;
  1457. }
  1458. dump_file = debugfs_create_file("dump_info",
  1459. 0400,
  1460. dir,
  1461. display,
  1462. &dump_info_fops);
  1463. if (IS_ERR_OR_NULL(dump_file)) {
  1464. rc = PTR_ERR(dump_file);
  1465. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1466. display->name, rc);
  1467. goto error_remove_dir;
  1468. }
  1469. dump_file = debugfs_create_file("esd_trigger",
  1470. 0644,
  1471. dir,
  1472. display,
  1473. &esd_trigger_fops);
  1474. if (IS_ERR_OR_NULL(dump_file)) {
  1475. rc = PTR_ERR(dump_file);
  1476. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1477. display->name, rc);
  1478. goto error_remove_dir;
  1479. }
  1480. dump_file = debugfs_create_file("esd_check_mode",
  1481. 0644,
  1482. dir,
  1483. display,
  1484. &esd_check_mode_fops);
  1485. if (IS_ERR_OR_NULL(dump_file)) {
  1486. rc = PTR_ERR(dump_file);
  1487. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1488. display->name, rc);
  1489. goto error_remove_dir;
  1490. }
  1491. dump_file = debugfs_create_file("cmd_sched_params",
  1492. 0644,
  1493. dir,
  1494. display,
  1495. &dsi_command_scheduling_fops);
  1496. if (IS_ERR_OR_NULL(dump_file)) {
  1497. rc = PTR_ERR(dump_file);
  1498. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1499. display->name, rc);
  1500. goto error_remove_dir;
  1501. }
  1502. misr_data = debugfs_create_file("misr_data",
  1503. 0600,
  1504. dir,
  1505. display,
  1506. &misr_data_fops);
  1507. if (IS_ERR_OR_NULL(misr_data)) {
  1508. rc = PTR_ERR(misr_data);
  1509. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1510. display->name, rc);
  1511. goto error_remove_dir;
  1512. }
  1513. display_for_each_ctrl(i, display) {
  1514. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1515. if (!phy || !phy->name)
  1516. continue;
  1517. snprintf(name, ARRAY_SIZE(name),
  1518. "%s_allow_phy_power_off", phy->name);
  1519. dump_file = debugfs_create_bool(name, 0600, dir,
  1520. &phy->allow_phy_power_off);
  1521. if (IS_ERR_OR_NULL(dump_file)) {
  1522. rc = PTR_ERR(dump_file);
  1523. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1524. display->name, name, rc);
  1525. goto error_remove_dir;
  1526. }
  1527. snprintf(name, ARRAY_SIZE(name),
  1528. "%s_regulator_min_datarate_bps", phy->name);
  1529. dump_file = debugfs_create_u32(name, 0600, dir,
  1530. &phy->regulator_min_datarate_bps);
  1531. if (IS_ERR_OR_NULL(dump_file)) {
  1532. rc = PTR_ERR(dump_file);
  1533. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1534. display->name, name, rc);
  1535. goto error_remove_dir;
  1536. }
  1537. }
  1538. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1539. &display->panel->ulps_feature_enabled)) {
  1540. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1541. display->name);
  1542. goto error_remove_dir;
  1543. }
  1544. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1545. &display->panel->ulps_suspend_enabled)) {
  1546. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1547. display->name);
  1548. goto error_remove_dir;
  1549. }
  1550. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1551. &display->ulps_enabled)) {
  1552. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1553. display->name);
  1554. goto error_remove_dir;
  1555. }
  1556. if (!debugfs_create_u32("clk_gating_config", 0600, dir,
  1557. &display->clk_gating_config)) {
  1558. DSI_ERR("[%s] debugfs create clk gating config failed\n",
  1559. display->name);
  1560. goto error_remove_dir;
  1561. }
  1562. display->root = dir;
  1563. dsi_parser_dbg_init(display->parser, dir);
  1564. return rc;
  1565. error_remove_dir:
  1566. debugfs_remove(dir);
  1567. error:
  1568. return rc;
  1569. }
  1570. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1571. {
  1572. debugfs_remove_recursive(display->root);
  1573. return 0;
  1574. }
  1575. #else
  1576. static int dsi_display_debugfs_init(struct dsi_display *display)
  1577. {
  1578. return 0;
  1579. }
  1580. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1581. {
  1582. return 0;
  1583. }
  1584. #endif /* CONFIG_DEBUG_FS */
  1585. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1586. struct dsi_display_mode *mode)
  1587. {
  1588. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1589. bool is_split_link = host->split_link.split_link_enabled;
  1590. u32 sublinks_count = host->split_link.num_sublinks;
  1591. if (is_split_link && sublinks_count > 1) {
  1592. mode->timing.h_active /= sublinks_count;
  1593. mode->timing.h_front_porch /= sublinks_count;
  1594. mode->timing.h_sync_width /= sublinks_count;
  1595. mode->timing.h_back_porch /= sublinks_count;
  1596. mode->timing.h_skew /= sublinks_count;
  1597. mode->pixel_clk_khz /= sublinks_count;
  1598. } else {
  1599. if (mode->priv_info->dsc_enabled)
  1600. mode->priv_info->dsc.config.pic_width =
  1601. mode->timing.h_active;
  1602. mode->timing.h_active /= display->ctrl_count;
  1603. mode->timing.h_front_porch /= display->ctrl_count;
  1604. mode->timing.h_sync_width /= display->ctrl_count;
  1605. mode->timing.h_back_porch /= display->ctrl_count;
  1606. mode->timing.h_skew /= display->ctrl_count;
  1607. mode->pixel_clk_khz /= display->ctrl_count;
  1608. }
  1609. }
  1610. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1611. bool enable)
  1612. {
  1613. /* TODO: make checks based on cont. splash */
  1614. DSI_DEBUG("checking ulps req validity\n");
  1615. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1616. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1617. return false;
  1618. }
  1619. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1620. !display->panel->ulps_suspend_enabled) {
  1621. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1622. return false;
  1623. }
  1624. if (!dsi_panel_initialized(display->panel) &&
  1625. !display->panel->ulps_suspend_enabled) {
  1626. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1627. return false;
  1628. }
  1629. if (enable && display->ulps_enabled) {
  1630. DSI_DEBUG("ULPS already enabled\n");
  1631. return false;
  1632. } else if (!enable && !display->ulps_enabled) {
  1633. DSI_DEBUG("ULPS already disabled\n");
  1634. return false;
  1635. }
  1636. /*
  1637. * No need to enter ULPS when transitioning from splash screen to
  1638. * boot animation or trusted vm environments since it is expected
  1639. * that the clocks would be turned right back on.
  1640. */
  1641. if (enable && is_skip_op_required(display))
  1642. return false;
  1643. return true;
  1644. }
  1645. /**
  1646. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1647. * @dsi_display: DSI display handle.
  1648. * @enable: enable/disable ULPS.
  1649. *
  1650. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1651. *
  1652. * Return: error code.
  1653. */
  1654. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1655. {
  1656. int rc = 0;
  1657. int i = 0;
  1658. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1659. if (!display) {
  1660. DSI_ERR("Invalid params\n");
  1661. return -EINVAL;
  1662. }
  1663. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1664. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1665. __func__, enable);
  1666. return 0;
  1667. }
  1668. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1669. /*
  1670. * ULPS entry-exit can be either through the DSI controller or
  1671. * the DSI PHY depending on hardware variation. For some chipsets,
  1672. * both controller version and phy version ulps entry-exit ops can
  1673. * be present. To handle such cases, send ulps request through PHY,
  1674. * if ulps request is handled in PHY, then no need to send request
  1675. * through controller.
  1676. */
  1677. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1678. display->clamp_enabled);
  1679. if (rc == DSI_PHY_ULPS_ERROR) {
  1680. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1681. return -EINVAL;
  1682. }
  1683. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1684. display_for_each_ctrl(i, display) {
  1685. ctrl = &display->ctrl[i];
  1686. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1687. continue;
  1688. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1689. enable, display->clamp_enabled);
  1690. if (rc == DSI_PHY_ULPS_ERROR) {
  1691. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1692. enable);
  1693. return -EINVAL;
  1694. }
  1695. }
  1696. }
  1697. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1698. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1699. if (rc) {
  1700. DSI_ERR("Ulps controller state change(%d) failed\n",
  1701. enable);
  1702. return rc;
  1703. }
  1704. display_for_each_ctrl(i, display) {
  1705. ctrl = &display->ctrl[i];
  1706. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1707. continue;
  1708. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1709. if (rc) {
  1710. DSI_ERR("Ulps controller state change(%d) failed\n",
  1711. enable);
  1712. return rc;
  1713. }
  1714. }
  1715. }
  1716. display->ulps_enabled = enable;
  1717. return 0;
  1718. }
  1719. /**
  1720. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1721. * @dsi_display: DSI display handle.
  1722. * @enable: enable/disable clamping.
  1723. *
  1724. * Return: error code.
  1725. */
  1726. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1727. {
  1728. int rc = 0;
  1729. int i = 0;
  1730. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1731. bool ulps_enabled = false;
  1732. if (!display) {
  1733. DSI_ERR("Invalid params\n");
  1734. return -EINVAL;
  1735. }
  1736. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1737. ulps_enabled = display->ulps_enabled;
  1738. /*
  1739. * Clamp control can be either through the DSI controller or
  1740. * the DSI PHY depending on hardware variation
  1741. */
  1742. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1743. if (rc) {
  1744. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1745. return rc;
  1746. }
  1747. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1748. if (rc) {
  1749. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1750. return rc;
  1751. }
  1752. display_for_each_ctrl(i, display) {
  1753. ctrl = &display->ctrl[i];
  1754. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1755. continue;
  1756. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1757. if (rc) {
  1758. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1759. return rc;
  1760. }
  1761. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1762. if (rc) {
  1763. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1764. enable);
  1765. return rc;
  1766. }
  1767. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1768. enable ? "enabled" : "disabled", i);
  1769. }
  1770. display->clamp_enabled = enable;
  1771. return 0;
  1772. }
  1773. /**
  1774. * dsi_display_setup_ctrl() - setup DSI controller.
  1775. * @dsi_display: DSI display handle.
  1776. *
  1777. * Return: error code.
  1778. */
  1779. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1780. {
  1781. int rc = 0;
  1782. int i = 0;
  1783. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1784. if (!display) {
  1785. DSI_ERR("Invalid params\n");
  1786. return -EINVAL;
  1787. }
  1788. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1789. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1790. if (rc) {
  1791. DSI_ERR("DSI controller setup failed\n");
  1792. return rc;
  1793. }
  1794. display_for_each_ctrl(i, display) {
  1795. ctrl = &display->ctrl[i];
  1796. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1797. continue;
  1798. rc = dsi_ctrl_setup(ctrl->ctrl);
  1799. if (rc) {
  1800. DSI_ERR("DSI controller setup failed\n");
  1801. return rc;
  1802. }
  1803. }
  1804. return 0;
  1805. }
  1806. static int dsi_display_phy_enable(struct dsi_display *display);
  1807. /**
  1808. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1809. * @dsi_display: DSI display handle.
  1810. * @mmss_clamp: True if clamp is enabled.
  1811. *
  1812. * Return: error code.
  1813. */
  1814. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1815. bool mmss_clamp)
  1816. {
  1817. int rc = 0;
  1818. int i = 0;
  1819. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1820. if (!display) {
  1821. DSI_ERR("Invalid params\n");
  1822. return -EINVAL;
  1823. }
  1824. if (mmss_clamp && !display->phy_idle_power_off) {
  1825. dsi_display_phy_enable(display);
  1826. return 0;
  1827. }
  1828. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1829. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1830. if (rc) {
  1831. DSI_ERR("DSI controller setup failed\n");
  1832. return rc;
  1833. }
  1834. display_for_each_ctrl(i, display) {
  1835. ctrl = &display->ctrl[i];
  1836. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1837. continue;
  1838. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1839. if (rc) {
  1840. DSI_ERR("DSI controller setup failed\n");
  1841. return rc;
  1842. }
  1843. }
  1844. display->phy_idle_power_off = false;
  1845. return 0;
  1846. }
  1847. /**
  1848. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  1849. * @dsi_display: DSI display handle.
  1850. *
  1851. * Return: error code.
  1852. */
  1853. static int dsi_display_phy_idle_off(struct dsi_display *display)
  1854. {
  1855. int rc = 0;
  1856. int i = 0;
  1857. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1858. if (!display) {
  1859. DSI_ERR("Invalid params\n");
  1860. return -EINVAL;
  1861. }
  1862. display_for_each_ctrl(i, display) {
  1863. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1864. if (!phy)
  1865. continue;
  1866. if (!phy->allow_phy_power_off) {
  1867. DSI_DEBUG("phy doesn't support this feature\n");
  1868. return 0;
  1869. }
  1870. }
  1871. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1872. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  1873. if (rc) {
  1874. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  1875. display->name, rc);
  1876. return rc;
  1877. }
  1878. display_for_each_ctrl(i, display) {
  1879. ctrl = &display->ctrl[i];
  1880. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1881. continue;
  1882. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  1883. if (rc) {
  1884. DSI_ERR("DSI controller setup failed\n");
  1885. return rc;
  1886. }
  1887. }
  1888. display->phy_idle_power_off = true;
  1889. return 0;
  1890. }
  1891. void dsi_display_enable_event(struct drm_connector *connector,
  1892. struct dsi_display *display,
  1893. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  1894. bool enable)
  1895. {
  1896. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  1897. int i;
  1898. if (!display) {
  1899. DSI_ERR("invalid display\n");
  1900. return;
  1901. }
  1902. if (event_info)
  1903. event_info->event_idx = event_idx;
  1904. switch (event_idx) {
  1905. case SDE_CONN_EVENT_VID_DONE:
  1906. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  1907. break;
  1908. case SDE_CONN_EVENT_CMD_DONE:
  1909. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  1910. break;
  1911. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  1912. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  1913. if (event_info) {
  1914. display_for_each_ctrl(i, display)
  1915. display->ctrl[i].ctrl->recovery_cb =
  1916. *event_info;
  1917. }
  1918. break;
  1919. case SDE_CONN_EVENT_PANEL_ID:
  1920. if (event_info)
  1921. display_for_each_ctrl(i, display)
  1922. display->ctrl[i].ctrl->panel_id_cb
  1923. = *event_info;
  1924. break;
  1925. default:
  1926. /* nothing to do */
  1927. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  1928. return;
  1929. }
  1930. if (enable) {
  1931. display_for_each_ctrl(i, display)
  1932. dsi_ctrl_enable_status_interrupt(
  1933. display->ctrl[i].ctrl, irq_status_idx,
  1934. event_info);
  1935. } else {
  1936. display_for_each_ctrl(i, display)
  1937. dsi_ctrl_disable_status_interrupt(
  1938. display->ctrl[i].ctrl, irq_status_idx);
  1939. }
  1940. }
  1941. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  1942. {
  1943. int rc = 0;
  1944. int i;
  1945. struct dsi_display_ctrl *ctrl;
  1946. /* Sequence does not matter for split dsi usecases */
  1947. display_for_each_ctrl(i, display) {
  1948. ctrl = &display->ctrl[i];
  1949. if (!ctrl->ctrl)
  1950. continue;
  1951. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  1952. DSI_CTRL_POWER_VREG_ON);
  1953. if (rc) {
  1954. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  1955. ctrl->ctrl->name, rc);
  1956. goto error;
  1957. }
  1958. }
  1959. return rc;
  1960. error:
  1961. for (i = i - 1; i >= 0; i--) {
  1962. ctrl = &display->ctrl[i];
  1963. if (!ctrl->ctrl)
  1964. continue;
  1965. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  1966. DSI_CTRL_POWER_VREG_OFF);
  1967. }
  1968. return rc;
  1969. }
  1970. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  1971. {
  1972. int rc = 0;
  1973. int i;
  1974. struct dsi_display_ctrl *ctrl;
  1975. /* Sequence does not matter for split dsi usecases */
  1976. display_for_each_ctrl(i, display) {
  1977. ctrl = &display->ctrl[i];
  1978. if (!ctrl->ctrl)
  1979. continue;
  1980. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  1981. DSI_CTRL_POWER_VREG_OFF);
  1982. if (rc) {
  1983. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  1984. ctrl->ctrl->name, rc);
  1985. goto error;
  1986. }
  1987. }
  1988. error:
  1989. return rc;
  1990. }
  1991. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  1992. unsigned int display_type)
  1993. {
  1994. char *boot_str = NULL;
  1995. char *str = NULL;
  1996. char *sw_te = NULL;
  1997. unsigned long cmdline_topology = NO_OVERRIDE;
  1998. unsigned long cmdline_timing = NO_OVERRIDE;
  1999. unsigned long panel_id = NO_OVERRIDE;
  2000. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2001. DSI_ERR("display_type=%d not supported\n", display_type);
  2002. goto end;
  2003. }
  2004. if (display_type == DSI_PRIMARY)
  2005. boot_str = dsi_display_primary;
  2006. else
  2007. boot_str = dsi_display_secondary;
  2008. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2009. if (sw_te)
  2010. display->sw_te_using_wd = true;
  2011. str = strnstr(boot_str, ":panelid", strlen(boot_str));
  2012. if (str) {
  2013. if (kstrtol(str + strlen(":panelid"), INT_BASE_10,
  2014. (unsigned long *)&panel_id)) {
  2015. DSI_INFO("panel id not found: %s\n", boot_str);
  2016. } else {
  2017. DSI_INFO("panel id found: %lx\n", panel_id);
  2018. display->panel_id = panel_id;
  2019. }
  2020. }
  2021. str = strnstr(boot_str, ":config", strlen(boot_str));
  2022. if (str) {
  2023. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2024. DSI_ERR("invalid config index override: %s\n",
  2025. boot_str);
  2026. goto end;
  2027. }
  2028. }
  2029. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2030. if (str) {
  2031. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2032. DSI_ERR("invalid timing index override: %s\n",
  2033. boot_str);
  2034. cmdline_topology = NO_OVERRIDE;
  2035. goto end;
  2036. }
  2037. }
  2038. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2039. end:
  2040. display->cmdline_topology = cmdline_topology;
  2041. display->cmdline_timing = cmdline_timing;
  2042. }
  2043. /**
  2044. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2045. *
  2046. * Return: returns error status
  2047. */
  2048. static int dsi_display_parse_boot_display_selection(void)
  2049. {
  2050. char *pos = NULL;
  2051. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2052. int i, j;
  2053. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2054. strlcpy(disp_buf, boot_displays[i].boot_param,
  2055. MAX_CMDLINE_PARAM_LEN);
  2056. pos = strnstr(disp_buf, ":", MAX_CMDLINE_PARAM_LEN);
  2057. /* Use ':' as a delimiter to retrieve the display name */
  2058. if (!pos) {
  2059. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2060. continue;
  2061. }
  2062. for (j = 0; (disp_buf + j) < pos; j++)
  2063. boot_displays[i].name[j] = *(disp_buf + j);
  2064. boot_displays[i].name[j] = '\0';
  2065. boot_displays[i].boot_disp_en = true;
  2066. }
  2067. return 0;
  2068. }
  2069. static int dsi_display_phy_power_on(struct dsi_display *display)
  2070. {
  2071. int rc = 0;
  2072. int i;
  2073. struct dsi_display_ctrl *ctrl;
  2074. /* Sequence does not matter for split dsi usecases */
  2075. display_for_each_ctrl(i, display) {
  2076. ctrl = &display->ctrl[i];
  2077. if (!ctrl->ctrl)
  2078. continue;
  2079. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2080. if (rc) {
  2081. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2082. ctrl->phy->name, rc);
  2083. goto error;
  2084. }
  2085. }
  2086. return rc;
  2087. error:
  2088. for (i = i - 1; i >= 0; i--) {
  2089. ctrl = &display->ctrl[i];
  2090. if (!ctrl->phy)
  2091. continue;
  2092. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2093. }
  2094. return rc;
  2095. }
  2096. static int dsi_display_phy_power_off(struct dsi_display *display)
  2097. {
  2098. int rc = 0;
  2099. int i;
  2100. struct dsi_display_ctrl *ctrl;
  2101. /* Sequence does not matter for split dsi usecases */
  2102. display_for_each_ctrl(i, display) {
  2103. ctrl = &display->ctrl[i];
  2104. if (!ctrl->phy)
  2105. continue;
  2106. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2107. if (rc) {
  2108. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2109. ctrl->ctrl->name, rc);
  2110. goto error;
  2111. }
  2112. }
  2113. error:
  2114. return rc;
  2115. }
  2116. static int dsi_display_set_clk_src(struct dsi_display *display)
  2117. {
  2118. int rc = 0;
  2119. int i;
  2120. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2121. /*
  2122. * For CPHY mode, the parent of mux_clks need to be set
  2123. * to Cphy_clks to have correct dividers for byte and
  2124. * pixel clocks.
  2125. */
  2126. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) {
  2127. rc = dsi_clk_update_parent(&display->clock_info.cphy_clks,
  2128. &display->clock_info.mux_clks);
  2129. if (rc) {
  2130. DSI_ERR("failed update mux parent to shadow\n");
  2131. return rc;
  2132. }
  2133. }
  2134. /*
  2135. * In case of split DSI usecases, the clock for master controller should
  2136. * be enabled before the other controller. Master controller in the
  2137. * clock context refers to the controller that sources the clock.
  2138. */
  2139. m_ctrl = &display->ctrl[display->clk_master_idx];
  2140. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
  2141. &display->clock_info.mux_clks);
  2142. if (rc) {
  2143. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n",
  2144. display->name, rc);
  2145. return rc;
  2146. }
  2147. /* Turn on rest of the controllers */
  2148. display_for_each_ctrl(i, display) {
  2149. ctrl = &display->ctrl[i];
  2150. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2151. continue;
  2152. rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
  2153. &display->clock_info.mux_clks);
  2154. if (rc) {
  2155. DSI_ERR("[%s] failed to set source clocks, rc=%d\n",
  2156. display->name, rc);
  2157. return rc;
  2158. }
  2159. }
  2160. return 0;
  2161. }
  2162. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2163. bool enable)
  2164. {
  2165. int rc = 0;
  2166. int i;
  2167. struct dsi_display_ctrl *ctrl;
  2168. display_for_each_ctrl(i, display) {
  2169. ctrl = &display->ctrl[i];
  2170. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2171. if (rc) {
  2172. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2173. display->name, enable ? "mask" : "unmask", rc);
  2174. return rc;
  2175. }
  2176. }
  2177. return 0;
  2178. }
  2179. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2180. {
  2181. struct dsi_display_ctrl *ctrl;
  2182. int i;
  2183. if (!display)
  2184. return;
  2185. display_for_each_ctrl(i, display) {
  2186. ctrl = &display->ctrl[i];
  2187. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2188. }
  2189. /*
  2190. * After retime buffer synchronization we need to turn of clk_en_sel
  2191. * bit on each phy. Avoid this for Cphy.
  2192. */
  2193. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2194. return;
  2195. display_for_each_ctrl(i, display) {
  2196. ctrl = &display->ctrl[i];
  2197. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2198. }
  2199. }
  2200. static int dsi_display_ctrl_update(struct dsi_display *display)
  2201. {
  2202. int rc = 0;
  2203. int i;
  2204. struct dsi_display_ctrl *ctrl;
  2205. display_for_each_ctrl(i, display) {
  2206. ctrl = &display->ctrl[i];
  2207. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2208. if (rc) {
  2209. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2210. display->name, i, rc);
  2211. goto error_host_deinit;
  2212. }
  2213. }
  2214. return 0;
  2215. error_host_deinit:
  2216. for (i = i - 1; i >= 0; i--) {
  2217. ctrl = &display->ctrl[i];
  2218. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2219. }
  2220. return rc;
  2221. }
  2222. static int dsi_display_ctrl_init(struct dsi_display *display)
  2223. {
  2224. int rc = 0;
  2225. int i;
  2226. struct dsi_display_ctrl *ctrl;
  2227. bool skip_op = is_skip_op_required(display);
  2228. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2229. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2230. * we will programe DSI controller as part of core clock enable.
  2231. * After that we should not re-configure DSI controller again here for
  2232. * usecases where we are resuming from ulps suspend as it might put
  2233. * the HW in bad state.
  2234. */
  2235. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2236. display_for_each_ctrl(i, display) {
  2237. ctrl = &display->ctrl[i];
  2238. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2239. if (rc) {
  2240. DSI_ERR(
  2241. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2242. display->name, i, skip_op, rc);
  2243. goto error_host_deinit;
  2244. }
  2245. }
  2246. } else {
  2247. display_for_each_ctrl(i, display) {
  2248. ctrl = &display->ctrl[i];
  2249. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2250. DSI_CTRL_OP_HOST_INIT,
  2251. true);
  2252. if (rc)
  2253. DSI_DEBUG("host init update failed rc=%d\n",
  2254. rc);
  2255. }
  2256. }
  2257. return rc;
  2258. error_host_deinit:
  2259. for (i = i - 1; i >= 0; i--) {
  2260. ctrl = &display->ctrl[i];
  2261. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2262. }
  2263. return rc;
  2264. }
  2265. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2266. {
  2267. int rc = 0;
  2268. int i;
  2269. struct dsi_display_ctrl *ctrl;
  2270. display_for_each_ctrl(i, display) {
  2271. ctrl = &display->ctrl[i];
  2272. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2273. if (rc) {
  2274. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2275. display->name, i, rc);
  2276. }
  2277. }
  2278. return rc;
  2279. }
  2280. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2281. {
  2282. int rc = 0;
  2283. int i;
  2284. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2285. bool skip_op = is_skip_op_required(display);
  2286. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2287. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2288. DSI_CTRL_ENGINE_ON, skip_op);
  2289. if (rc) {
  2290. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2291. display->name, skip_op, rc);
  2292. goto error;
  2293. }
  2294. display_for_each_ctrl(i, display) {
  2295. ctrl = &display->ctrl[i];
  2296. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2297. continue;
  2298. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2299. DSI_CTRL_ENGINE_ON, skip_op);
  2300. if (rc) {
  2301. DSI_ERR(
  2302. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2303. display->name, skip_op, rc);
  2304. goto error_disable_master;
  2305. }
  2306. }
  2307. return rc;
  2308. error_disable_master:
  2309. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2310. DSI_CTRL_ENGINE_OFF, skip_op);
  2311. error:
  2312. return rc;
  2313. }
  2314. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2315. {
  2316. int rc = 0;
  2317. int i;
  2318. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2319. bool skip_op = is_skip_op_required(display);
  2320. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2321. /*
  2322. * For platforms where ULPS is controlled by DSI controller block,
  2323. * do not disable dsi controller block if lanes are to be
  2324. * kept in ULPS during suspend. So just update the SW state
  2325. * and return early.
  2326. */
  2327. if (display->panel->ulps_suspend_enabled &&
  2328. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2329. display_for_each_ctrl(i, display) {
  2330. ctrl = &display->ctrl[i];
  2331. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2332. DSI_CTRL_OP_HOST_ENGINE,
  2333. false);
  2334. if (rc)
  2335. DSI_DEBUG("host state update failed %d\n", rc);
  2336. }
  2337. return rc;
  2338. }
  2339. display_for_each_ctrl(i, display) {
  2340. ctrl = &display->ctrl[i];
  2341. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2342. continue;
  2343. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2344. DSI_CTRL_ENGINE_OFF, skip_op);
  2345. if (rc)
  2346. DSI_ERR(
  2347. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2348. display->name, skip_op, rc);
  2349. }
  2350. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2351. DSI_CTRL_ENGINE_OFF, skip_op);
  2352. if (rc) {
  2353. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2354. display->name, skip_op, rc);
  2355. goto error;
  2356. }
  2357. error:
  2358. return rc;
  2359. }
  2360. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2361. {
  2362. int rc = 0;
  2363. int i;
  2364. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2365. bool skip_op = is_skip_op_required(display);
  2366. m_ctrl = &display->ctrl[display->video_master_idx];
  2367. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2368. DSI_CTRL_ENGINE_ON, skip_op);
  2369. if (rc) {
  2370. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2371. display->name, skip_op, rc);
  2372. goto error;
  2373. }
  2374. display_for_each_ctrl(i, display) {
  2375. ctrl = &display->ctrl[i];
  2376. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2377. continue;
  2378. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2379. DSI_CTRL_ENGINE_ON, skip_op);
  2380. if (rc) {
  2381. DSI_ERR(
  2382. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2383. display->name, skip_op, rc);
  2384. goto error_disable_master;
  2385. }
  2386. }
  2387. return rc;
  2388. error_disable_master:
  2389. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2390. DSI_CTRL_ENGINE_OFF, skip_op);
  2391. error:
  2392. return rc;
  2393. }
  2394. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2395. {
  2396. int rc = 0;
  2397. int i;
  2398. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2399. bool skip_op = is_skip_op_required(display);
  2400. m_ctrl = &display->ctrl[display->video_master_idx];
  2401. display_for_each_ctrl(i, display) {
  2402. ctrl = &display->ctrl[i];
  2403. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2404. continue;
  2405. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2406. DSI_CTRL_ENGINE_OFF, skip_op);
  2407. if (rc)
  2408. DSI_ERR(
  2409. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2410. display->name, skip_op, rc);
  2411. }
  2412. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2413. DSI_CTRL_ENGINE_OFF, skip_op);
  2414. if (rc)
  2415. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2416. display->name, skip_op, rc);
  2417. return rc;
  2418. }
  2419. static int dsi_display_phy_enable(struct dsi_display *display)
  2420. {
  2421. int rc = 0;
  2422. int i;
  2423. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2424. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2425. bool skip_op = is_skip_op_required(display);
  2426. m_ctrl = &display->ctrl[display->clk_master_idx];
  2427. if (display->ctrl_count > 1)
  2428. m_src = DSI_PLL_SOURCE_NATIVE;
  2429. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2430. m_src, true, skip_op);
  2431. if (rc) {
  2432. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2433. display->name, skip_op, rc);
  2434. goto error;
  2435. }
  2436. display_for_each_ctrl(i, display) {
  2437. ctrl = &display->ctrl[i];
  2438. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2439. continue;
  2440. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2441. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2442. if (rc) {
  2443. DSI_ERR(
  2444. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2445. display->name, skip_op, rc);
  2446. goto error_disable_master;
  2447. }
  2448. }
  2449. return rc;
  2450. error_disable_master:
  2451. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2452. error:
  2453. return rc;
  2454. }
  2455. static int dsi_display_phy_disable(struct dsi_display *display)
  2456. {
  2457. int rc = 0;
  2458. int i;
  2459. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2460. bool skip_op = is_skip_op_required(display);
  2461. m_ctrl = &display->ctrl[display->clk_master_idx];
  2462. display_for_each_ctrl(i, display) {
  2463. ctrl = &display->ctrl[i];
  2464. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2465. continue;
  2466. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2467. if (rc)
  2468. DSI_ERR(
  2469. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2470. display->name, skip_op, rc);
  2471. }
  2472. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2473. if (rc)
  2474. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2475. display->name, skip_op, rc);
  2476. return rc;
  2477. }
  2478. static int dsi_display_wake_up(struct dsi_display *display)
  2479. {
  2480. return 0;
  2481. }
  2482. static int dsi_display_broadcast_cmd(struct dsi_display *display,
  2483. const struct mipi_dsi_msg *msg)
  2484. {
  2485. int rc = 0;
  2486. u32 flags, m_flags;
  2487. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2488. int i;
  2489. m_flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_BROADCAST_MASTER |
  2490. DSI_CTRL_CMD_DEFER_TRIGGER | DSI_CTRL_CMD_FETCH_MEMORY);
  2491. flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER |
  2492. DSI_CTRL_CMD_FETCH_MEMORY);
  2493. if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) {
  2494. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  2495. m_flags |= DSI_CTRL_CMD_LAST_COMMAND;
  2496. }
  2497. if ((msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  2498. (display->panel->panel_initialized)) {
  2499. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2500. m_flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2501. }
  2502. if (display->queue_cmd_waits ||
  2503. msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE) {
  2504. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2505. m_flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2506. }
  2507. /*
  2508. * 1. Setup commands in FIFO
  2509. * 2. Trigger commands
  2510. */
  2511. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2512. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, msg, &m_flags);
  2513. if (rc) {
  2514. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2515. display->name, rc);
  2516. goto error;
  2517. }
  2518. display_for_each_ctrl(i, display) {
  2519. ctrl = &display->ctrl[i];
  2520. if (ctrl == m_ctrl)
  2521. continue;
  2522. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, msg, &flags);
  2523. if (rc) {
  2524. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2525. display->name, rc);
  2526. goto error;
  2527. }
  2528. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, flags);
  2529. if (rc) {
  2530. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2531. display->name, rc);
  2532. goto error;
  2533. }
  2534. }
  2535. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, m_flags);
  2536. if (rc) {
  2537. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2538. display->name, rc);
  2539. goto error;
  2540. }
  2541. error:
  2542. return rc;
  2543. }
  2544. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2545. {
  2546. int rc = 0;
  2547. int i;
  2548. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2549. /*
  2550. * For continuous splash and trusted vm environment,
  2551. * ctrl states are updated separately and hence we do
  2552. * an early return
  2553. */
  2554. if (is_skip_op_required(display)) {
  2555. DSI_DEBUG(
  2556. "cont splash/trusted vm use case, phy sw reset not required\n");
  2557. return 0;
  2558. }
  2559. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2560. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2561. if (rc) {
  2562. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2563. goto error;
  2564. }
  2565. display_for_each_ctrl(i, display) {
  2566. ctrl = &display->ctrl[i];
  2567. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2568. continue;
  2569. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2570. if (rc) {
  2571. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2572. display->name, rc);
  2573. goto error;
  2574. }
  2575. }
  2576. error:
  2577. return rc;
  2578. }
  2579. static int dsi_host_attach(struct mipi_dsi_host *host,
  2580. struct mipi_dsi_device *dsi)
  2581. {
  2582. return 0;
  2583. }
  2584. static int dsi_host_detach(struct mipi_dsi_host *host,
  2585. struct mipi_dsi_device *dsi)
  2586. {
  2587. return 0;
  2588. }
  2589. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
  2590. const struct mipi_dsi_msg *msg)
  2591. {
  2592. struct dsi_display *display;
  2593. int rc = 0, ret = 0;
  2594. if (!host || !msg) {
  2595. DSI_ERR("Invalid params\n");
  2596. return 0;
  2597. }
  2598. display = to_dsi_display(host);
  2599. /* Avoid sending DCS commands when ESD recovery is pending */
  2600. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2601. DSI_DEBUG("ESD recovery pending\n");
  2602. return 0;
  2603. }
  2604. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2605. DSI_ALL_CLKS, DSI_CLK_ON);
  2606. if (rc) {
  2607. DSI_ERR("[%s] failed to enable all DSI clocks, rc=%d\n",
  2608. display->name, rc);
  2609. goto error;
  2610. }
  2611. rc = dsi_display_wake_up(display);
  2612. if (rc) {
  2613. DSI_ERR("[%s] failed to wake up display, rc=%d\n",
  2614. display->name, rc);
  2615. goto error_disable_clks;
  2616. }
  2617. rc = dsi_display_cmd_engine_enable(display);
  2618. if (rc) {
  2619. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2620. display->name, rc);
  2621. goto error_disable_clks;
  2622. }
  2623. if (display->tx_cmd_buf == NULL) {
  2624. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2625. if (rc) {
  2626. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2627. goto error_disable_cmd_engine;
  2628. }
  2629. }
  2630. if (display->ctrl_count > 1 && !(msg->flags & MIPI_DSI_MSG_UNICAST)) {
  2631. rc = dsi_display_broadcast_cmd(display, msg);
  2632. if (rc) {
  2633. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n",
  2634. display->name, rc);
  2635. goto error_disable_cmd_engine;
  2636. }
  2637. } else {
  2638. int ctrl_idx = (msg->flags & MIPI_DSI_MSG_UNICAST) ?
  2639. msg->ctrl : 0;
  2640. u32 cmd_flags = DSI_CTRL_CMD_FETCH_MEMORY;
  2641. if (display->queue_cmd_waits ||
  2642. msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  2643. cmd_flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2644. if ((msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  2645. (display->panel->panel_initialized))
  2646. cmd_flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2647. rc = dsi_ctrl_cmd_transfer(display->ctrl[ctrl_idx].ctrl, msg,
  2648. &cmd_flags);
  2649. if (rc) {
  2650. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2651. display->name, rc);
  2652. goto error_disable_cmd_engine;
  2653. }
  2654. }
  2655. error_disable_cmd_engine:
  2656. ret = dsi_display_cmd_engine_disable(display);
  2657. if (ret) {
  2658. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  2659. display->name, ret);
  2660. }
  2661. error_disable_clks:
  2662. ret = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2663. DSI_ALL_CLKS, DSI_CLK_OFF);
  2664. if (ret) {
  2665. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  2666. display->name, ret);
  2667. }
  2668. error:
  2669. return rc;
  2670. }
  2671. static struct mipi_dsi_host_ops dsi_host_ops = {
  2672. .attach = dsi_host_attach,
  2673. .detach = dsi_host_detach,
  2674. .transfer = dsi_host_transfer,
  2675. };
  2676. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2677. {
  2678. int rc = 0;
  2679. struct mipi_dsi_host *host = &display->host;
  2680. host->dev = &display->pdev->dev;
  2681. host->ops = &dsi_host_ops;
  2682. rc = mipi_dsi_host_register(host);
  2683. if (rc) {
  2684. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2685. display->name, rc);
  2686. goto error;
  2687. }
  2688. error:
  2689. return rc;
  2690. }
  2691. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2692. {
  2693. int rc = 0;
  2694. struct mipi_dsi_host *host = &display->host;
  2695. mipi_dsi_host_unregister(host);
  2696. host->dev = NULL;
  2697. host->ops = NULL;
  2698. return rc;
  2699. }
  2700. static int dsi_display_clocks_deinit(struct dsi_display *display)
  2701. {
  2702. int rc = 0;
  2703. struct dsi_clk_link_set *src = &display->clock_info.src_clks;
  2704. struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
  2705. struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
  2706. if (src->byte_clk) {
  2707. devm_clk_put(&display->pdev->dev, src->byte_clk);
  2708. src->byte_clk = NULL;
  2709. }
  2710. if (src->pixel_clk) {
  2711. devm_clk_put(&display->pdev->dev, src->pixel_clk);
  2712. src->pixel_clk = NULL;
  2713. }
  2714. if (mux->byte_clk) {
  2715. devm_clk_put(&display->pdev->dev, mux->byte_clk);
  2716. mux->byte_clk = NULL;
  2717. }
  2718. if (mux->pixel_clk) {
  2719. devm_clk_put(&display->pdev->dev, mux->pixel_clk);
  2720. mux->pixel_clk = NULL;
  2721. }
  2722. if (shadow->byte_clk) {
  2723. devm_clk_put(&display->pdev->dev, shadow->byte_clk);
  2724. shadow->byte_clk = NULL;
  2725. }
  2726. if (shadow->pixel_clk) {
  2727. devm_clk_put(&display->pdev->dev, shadow->pixel_clk);
  2728. shadow->pixel_clk = NULL;
  2729. }
  2730. return rc;
  2731. }
  2732. static bool dsi_display_check_prefix(const char *clk_prefix,
  2733. const char *clk_name)
  2734. {
  2735. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2736. }
  2737. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2738. char *dsi_clk_name)
  2739. {
  2740. if (display->fw)
  2741. return dsi_parser_count_strings(display->parser_node,
  2742. dsi_clk_name);
  2743. else
  2744. return of_property_count_strings(display->panel_node,
  2745. dsi_clk_name);
  2746. }
  2747. static void dsi_display_get_clock_name(struct dsi_display *display,
  2748. char *dsi_clk_name, int index,
  2749. const char **clk_name)
  2750. {
  2751. if (display->fw)
  2752. dsi_parser_read_string_index(display->parser_node,
  2753. dsi_clk_name, index, clk_name);
  2754. else
  2755. of_property_read_string_index(display->panel_node,
  2756. dsi_clk_name, index, clk_name);
  2757. }
  2758. static int dsi_display_clocks_init(struct dsi_display *display)
  2759. {
  2760. int i, rc = 0, num_clk = 0;
  2761. const char *clk_name;
  2762. const char *src_byte = "src_byte", *src_pixel = "src_pixel";
  2763. const char *mux_byte = "mux_byte", *mux_pixel = "mux_pixel";
  2764. const char *cphy_byte = "cphy_byte", *cphy_pixel = "cphy_pixel";
  2765. const char *shadow_byte = "shadow_byte", *shadow_pixel = "shadow_pixel";
  2766. struct clk *dsi_clk;
  2767. struct dsi_clk_link_set *src = &display->clock_info.src_clks;
  2768. struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
  2769. struct dsi_clk_link_set *cphy = &display->clock_info.cphy_clks;
  2770. struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
  2771. struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);
  2772. char *dsi_clock_name;
  2773. if (!strcmp(display->display_type, "primary"))
  2774. dsi_clock_name = "qcom,dsi-select-clocks";
  2775. else
  2776. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2777. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2778. DSI_DEBUG("clk count=%d\n", num_clk);
  2779. for (i = 0; i < num_clk; i++) {
  2780. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2781. &clk_name);
  2782. DSI_DEBUG("clock name:%s\n", clk_name);
  2783. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2784. if (IS_ERR_OR_NULL(dsi_clk)) {
  2785. rc = PTR_ERR(dsi_clk);
  2786. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2787. if (dsi_display_check_prefix(mux_byte, clk_name)) {
  2788. mux->byte_clk = NULL;
  2789. goto error;
  2790. }
  2791. if (dsi_display_check_prefix(mux_pixel, clk_name)) {
  2792. mux->pixel_clk = NULL;
  2793. goto error;
  2794. }
  2795. if (dsi_display_check_prefix(cphy_byte, clk_name)) {
  2796. cphy->byte_clk = NULL;
  2797. goto error;
  2798. }
  2799. if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
  2800. cphy->pixel_clk = NULL;
  2801. goto error;
  2802. }
  2803. if (dyn_clk_caps->dyn_clk_support &&
  2804. (display->panel->panel_mode ==
  2805. DSI_OP_VIDEO_MODE)) {
  2806. if (dsi_display_check_prefix(src_byte,
  2807. clk_name))
  2808. src->byte_clk = NULL;
  2809. if (dsi_display_check_prefix(src_pixel,
  2810. clk_name))
  2811. src->pixel_clk = NULL;
  2812. if (dsi_display_check_prefix(shadow_byte,
  2813. clk_name))
  2814. shadow->byte_clk = NULL;
  2815. if (dsi_display_check_prefix(shadow_pixel,
  2816. clk_name))
  2817. shadow->pixel_clk = NULL;
  2818. dyn_clk_caps->dyn_clk_support = false;
  2819. }
  2820. }
  2821. if (dsi_display_check_prefix(src_byte, clk_name)) {
  2822. src->byte_clk = dsi_clk;
  2823. continue;
  2824. }
  2825. if (dsi_display_check_prefix(src_pixel, clk_name)) {
  2826. src->pixel_clk = dsi_clk;
  2827. continue;
  2828. }
  2829. if (dsi_display_check_prefix(cphy_byte, clk_name)) {
  2830. cphy->byte_clk = dsi_clk;
  2831. continue;
  2832. }
  2833. if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
  2834. cphy->pixel_clk = dsi_clk;
  2835. continue;
  2836. }
  2837. if (dsi_display_check_prefix(mux_byte, clk_name)) {
  2838. mux->byte_clk = dsi_clk;
  2839. continue;
  2840. }
  2841. if (dsi_display_check_prefix(mux_pixel, clk_name)) {
  2842. mux->pixel_clk = dsi_clk;
  2843. continue;
  2844. }
  2845. if (dsi_display_check_prefix(shadow_byte, clk_name)) {
  2846. shadow->byte_clk = dsi_clk;
  2847. continue;
  2848. }
  2849. if (dsi_display_check_prefix(shadow_pixel, clk_name)) {
  2850. shadow->pixel_clk = dsi_clk;
  2851. continue;
  2852. }
  2853. }
  2854. return 0;
  2855. error:
  2856. (void)dsi_display_clocks_deinit(display);
  2857. return rc;
  2858. }
  2859. static int dsi_display_clk_ctrl_cb(void *priv,
  2860. struct dsi_clk_ctrl_info clk_state_info)
  2861. {
  2862. int rc = 0;
  2863. struct dsi_display *display = NULL;
  2864. void *clk_handle = NULL;
  2865. if (!priv) {
  2866. DSI_ERR("Invalid params\n");
  2867. return -EINVAL;
  2868. }
  2869. display = priv;
  2870. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2871. clk_handle = display->mdp_clk_handle;
  2872. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2873. clk_handle = display->dsi_clk_handle;
  2874. } else {
  2875. DSI_ERR("invalid clk handle, return error\n");
  2876. return -EINVAL;
  2877. }
  2878. /*
  2879. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2880. * to turn off DSI clocks.
  2881. */
  2882. rc = dsi_display_clk_ctrl(clk_handle,
  2883. clk_state_info.clk_type, clk_state_info.clk_state);
  2884. if (rc) {
  2885. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2886. display->name, clk_state_info.clk_state,
  2887. clk_state_info.clk_type, rc);
  2888. return rc;
  2889. }
  2890. return 0;
  2891. }
  2892. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  2893. {
  2894. int i;
  2895. struct dsi_display_ctrl *ctrl;
  2896. if (!display)
  2897. return;
  2898. display_for_each_ctrl(i, display) {
  2899. ctrl = &display->ctrl[i];
  2900. if (!ctrl)
  2901. continue;
  2902. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  2903. }
  2904. }
  2905. int dsi_pre_clkoff_cb(void *priv,
  2906. enum dsi_clk_type clk,
  2907. enum dsi_lclk_type l_type,
  2908. enum dsi_clk_state new_state)
  2909. {
  2910. int rc = 0, i;
  2911. struct dsi_display *display = priv;
  2912. struct dsi_display_ctrl *ctrl;
  2913. /*
  2914. * If Idle Power Collapse occurs immediately after a CMD
  2915. * transfer with an asynchronous wait for DMA done, ensure
  2916. * that the work queued is scheduled and completed before turning
  2917. * off the clocks and disabling interrupts to validate the command
  2918. * transfer.
  2919. */
  2920. display_for_each_ctrl(i, display) {
  2921. ctrl = &display->ctrl[i];
  2922. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  2923. continue;
  2924. flush_workqueue(display->dma_cmd_workq);
  2925. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  2926. ctrl->ctrl->dma_wait_queued = false;
  2927. }
  2928. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2929. (l_type & DSI_LINK_LP_CLK)) {
  2930. /*
  2931. * If continuous clock is enabled then disable it
  2932. * before entering into ULPS Mode.
  2933. */
  2934. if (display->panel->host_config.force_hs_clk_lane)
  2935. _dsi_display_continuous_clk_ctrl(display, false);
  2936. /*
  2937. * If ULPS feature is enabled, enter ULPS first.
  2938. * However, when blanking the panel, we should enter ULPS
  2939. * only if ULPS during suspend feature is enabled.
  2940. */
  2941. if (!dsi_panel_initialized(display->panel)) {
  2942. if (display->panel->ulps_suspend_enabled)
  2943. rc = dsi_display_set_ulps(display, true);
  2944. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  2945. rc = dsi_display_set_ulps(display, true);
  2946. }
  2947. if (rc)
  2948. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  2949. __func__, rc);
  2950. }
  2951. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2952. (l_type & DSI_LINK_HS_CLK)) {
  2953. /*
  2954. * PHY clock gating should be disabled before the PLL and the
  2955. * branch clocks are turned off. Otherwise, it is possible that
  2956. * the clock RCGs may not be turned off correctly resulting
  2957. * in clock warnings.
  2958. */
  2959. rc = dsi_display_config_clk_gating(display, false);
  2960. if (rc)
  2961. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  2962. display->name, rc);
  2963. }
  2964. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  2965. /*
  2966. * Enable DSI clamps only if entering idle power collapse or
  2967. * when ULPS during suspend is enabled..
  2968. */
  2969. if (dsi_panel_initialized(display->panel) ||
  2970. display->panel->ulps_suspend_enabled) {
  2971. dsi_display_phy_idle_off(display);
  2972. rc = dsi_display_set_clamp(display, true);
  2973. if (rc)
  2974. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  2975. __func__, rc);
  2976. rc = dsi_display_phy_reset_config(display, false);
  2977. if (rc)
  2978. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  2979. __func__, rc);
  2980. } else {
  2981. /* Make sure that controller is not in ULPS state when
  2982. * the DSI link is not active.
  2983. */
  2984. rc = dsi_display_set_ulps(display, false);
  2985. if (rc)
  2986. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  2987. __func__, rc);
  2988. }
  2989. /* dsi will not be able to serve irqs from here on */
  2990. dsi_display_ctrl_irq_update(display, false);
  2991. /* cache the MISR values */
  2992. display_for_each_ctrl(i, display) {
  2993. ctrl = &display->ctrl[i];
  2994. if (!ctrl->ctrl)
  2995. continue;
  2996. dsi_ctrl_cache_misr(ctrl->ctrl);
  2997. }
  2998. }
  2999. return rc;
  3000. }
  3001. int dsi_post_clkon_cb(void *priv,
  3002. enum dsi_clk_type clk,
  3003. enum dsi_lclk_type l_type,
  3004. enum dsi_clk_state curr_state)
  3005. {
  3006. int rc = 0;
  3007. struct dsi_display *display = priv;
  3008. bool mmss_clamp = false;
  3009. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3010. mmss_clamp = display->clamp_enabled;
  3011. /*
  3012. * controller setup is needed if coming out of idle
  3013. * power collapse with clamps enabled.
  3014. */
  3015. if (mmss_clamp)
  3016. dsi_display_ctrl_setup(display);
  3017. /*
  3018. * Phy setup is needed if coming out of idle
  3019. * power collapse with clamps enabled.
  3020. */
  3021. if (display->phy_idle_power_off || mmss_clamp)
  3022. dsi_display_phy_idle_on(display, mmss_clamp);
  3023. if (display->ulps_enabled && mmss_clamp) {
  3024. /*
  3025. * ULPS Entry Request. This is needed if the lanes were
  3026. * in ULPS prior to power collapse, since after
  3027. * power collapse and reset, the DSI controller resets
  3028. * back to idle state and not ULPS. This ulps entry
  3029. * request will transition the state of the DSI
  3030. * controller to ULPS which will match the state of the
  3031. * DSI phy. This needs to be done prior to disabling
  3032. * the DSI clamps.
  3033. *
  3034. * Also, reset the ulps flag so that ulps_config
  3035. * function would reconfigure the controller state to
  3036. * ULPS.
  3037. */
  3038. display->ulps_enabled = false;
  3039. rc = dsi_display_set_ulps(display, true);
  3040. if (rc) {
  3041. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3042. __func__, rc);
  3043. goto error;
  3044. }
  3045. }
  3046. rc = dsi_display_phy_reset_config(display, true);
  3047. if (rc) {
  3048. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3049. __func__, rc);
  3050. goto error;
  3051. }
  3052. rc = dsi_display_set_clamp(display, false);
  3053. if (rc) {
  3054. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3055. __func__, rc);
  3056. goto error;
  3057. }
  3058. }
  3059. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3060. /*
  3061. * Toggle the resync FIFO everytime clock changes, except
  3062. * when cont-splash screen transition is going on.
  3063. * Toggling resync FIFO during cont splash transition
  3064. * can lead to blinks on the display.
  3065. */
  3066. if (!display->is_cont_splash_enabled)
  3067. dsi_display_toggle_resync_fifo(display);
  3068. if (display->ulps_enabled) {
  3069. rc = dsi_display_set_ulps(display, false);
  3070. if (rc) {
  3071. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3072. __func__, rc);
  3073. goto error;
  3074. }
  3075. }
  3076. if (display->panel->host_config.force_hs_clk_lane)
  3077. _dsi_display_continuous_clk_ctrl(display, true);
  3078. rc = dsi_display_config_clk_gating(display, true);
  3079. if (rc) {
  3080. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3081. display->name, rc);
  3082. goto error;
  3083. }
  3084. }
  3085. /* enable dsi to serve irqs */
  3086. if (clk & DSI_CORE_CLK)
  3087. dsi_display_ctrl_irq_update(display, true);
  3088. error:
  3089. return rc;
  3090. }
  3091. int dsi_post_clkoff_cb(void *priv,
  3092. enum dsi_clk_type clk_type,
  3093. enum dsi_lclk_type l_type,
  3094. enum dsi_clk_state curr_state)
  3095. {
  3096. int rc = 0;
  3097. struct dsi_display *display = priv;
  3098. if (!display) {
  3099. DSI_ERR("%s: Invalid arg\n", __func__);
  3100. return -EINVAL;
  3101. }
  3102. if ((clk_type & DSI_CORE_CLK) &&
  3103. (curr_state == DSI_CLK_OFF)) {
  3104. rc = dsi_display_phy_power_off(display);
  3105. if (rc)
  3106. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3107. display->name, rc);
  3108. rc = dsi_display_ctrl_power_off(display);
  3109. if (rc)
  3110. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3111. display->name, rc);
  3112. }
  3113. return rc;
  3114. }
  3115. int dsi_pre_clkon_cb(void *priv,
  3116. enum dsi_clk_type clk_type,
  3117. enum dsi_lclk_type l_type,
  3118. enum dsi_clk_state new_state)
  3119. {
  3120. int rc = 0;
  3121. struct dsi_display *display = priv;
  3122. if (!display) {
  3123. DSI_ERR("%s: invalid input\n", __func__);
  3124. return -EINVAL;
  3125. }
  3126. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3127. /*
  3128. * Enable DSI core power
  3129. * 1.> PANEL_PM are controlled as part of
  3130. * panel_power_ctrl. Needed not be handled here.
  3131. * 2.> CORE_PM are controlled by dsi clk manager.
  3132. * 3.> CTRL_PM need to be enabled/disabled
  3133. * only during unblank/blank. Their state should
  3134. * not be changed during static screen.
  3135. */
  3136. DSI_DEBUG("updating power states for ctrl and phy\n");
  3137. rc = dsi_display_ctrl_power_on(display);
  3138. if (rc) {
  3139. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3140. display->name, rc);
  3141. return rc;
  3142. }
  3143. rc = dsi_display_phy_power_on(display);
  3144. if (rc) {
  3145. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3146. display->name, rc);
  3147. return rc;
  3148. }
  3149. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3150. }
  3151. return rc;
  3152. }
  3153. static void __set_lane_map_v2(u8 *lane_map_v2,
  3154. enum dsi_phy_data_lanes lane0,
  3155. enum dsi_phy_data_lanes lane1,
  3156. enum dsi_phy_data_lanes lane2,
  3157. enum dsi_phy_data_lanes lane3)
  3158. {
  3159. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3160. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3161. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3162. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3163. }
  3164. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3165. {
  3166. int rc = 0, i = 0;
  3167. const char *data;
  3168. u8 temp[DSI_LANE_MAX - 1];
  3169. if (!display) {
  3170. DSI_ERR("invalid params\n");
  3171. return -EINVAL;
  3172. }
  3173. /* lane-map-v2 supersedes lane-map-v1 setting */
  3174. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3175. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3176. if (!rc) {
  3177. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3178. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3179. return 0;
  3180. } else if (rc != EINVAL) {
  3181. DSI_DEBUG("Incorrect mapping, configure default\n");
  3182. goto set_default;
  3183. }
  3184. /* lane-map older version, for DSI controller version < 2.0 */
  3185. data = of_get_property(display->pdev->dev.of_node,
  3186. "qcom,lane-map", NULL);
  3187. if (!data)
  3188. goto set_default;
  3189. if (!strcmp(data, "lane_map_3012")) {
  3190. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3191. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3192. DSI_PHYSICAL_LANE_1,
  3193. DSI_PHYSICAL_LANE_2,
  3194. DSI_PHYSICAL_LANE_3,
  3195. DSI_PHYSICAL_LANE_0);
  3196. } else if (!strcmp(data, "lane_map_2301")) {
  3197. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3198. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3199. DSI_PHYSICAL_LANE_2,
  3200. DSI_PHYSICAL_LANE_3,
  3201. DSI_PHYSICAL_LANE_0,
  3202. DSI_PHYSICAL_LANE_1);
  3203. } else if (!strcmp(data, "lane_map_1230")) {
  3204. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3205. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3206. DSI_PHYSICAL_LANE_3,
  3207. DSI_PHYSICAL_LANE_0,
  3208. DSI_PHYSICAL_LANE_1,
  3209. DSI_PHYSICAL_LANE_2);
  3210. } else if (!strcmp(data, "lane_map_0321")) {
  3211. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3212. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3213. DSI_PHYSICAL_LANE_0,
  3214. DSI_PHYSICAL_LANE_3,
  3215. DSI_PHYSICAL_LANE_2,
  3216. DSI_PHYSICAL_LANE_1);
  3217. } else if (!strcmp(data, "lane_map_1032")) {
  3218. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3219. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3220. DSI_PHYSICAL_LANE_1,
  3221. DSI_PHYSICAL_LANE_0,
  3222. DSI_PHYSICAL_LANE_3,
  3223. DSI_PHYSICAL_LANE_2);
  3224. } else if (!strcmp(data, "lane_map_2103")) {
  3225. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3226. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3227. DSI_PHYSICAL_LANE_2,
  3228. DSI_PHYSICAL_LANE_1,
  3229. DSI_PHYSICAL_LANE_0,
  3230. DSI_PHYSICAL_LANE_3);
  3231. } else if (!strcmp(data, "lane_map_3210")) {
  3232. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3233. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3234. DSI_PHYSICAL_LANE_3,
  3235. DSI_PHYSICAL_LANE_2,
  3236. DSI_PHYSICAL_LANE_1,
  3237. DSI_PHYSICAL_LANE_0);
  3238. } else {
  3239. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3240. __func__, data);
  3241. goto set_default;
  3242. }
  3243. return 0;
  3244. set_default:
  3245. /* default lane mapping */
  3246. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3247. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3248. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3249. return 0;
  3250. }
  3251. static int dsi_display_get_phandle_index(
  3252. struct dsi_display *display,
  3253. const char *propname, int count, int index)
  3254. {
  3255. struct device_node *disp_node = display->panel_node;
  3256. u32 *val = NULL;
  3257. int rc = 0;
  3258. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3259. if (ZERO_OR_NULL_PTR(val)) {
  3260. rc = -ENOMEM;
  3261. goto end;
  3262. }
  3263. if (index >= count)
  3264. goto end;
  3265. if (display->fw)
  3266. rc = dsi_parser_read_u32_array(display->parser_node,
  3267. propname, val, count);
  3268. else
  3269. rc = of_property_read_u32_array(disp_node, propname,
  3270. val, count);
  3271. if (rc)
  3272. goto end;
  3273. rc = val[index];
  3274. DSI_DEBUG("%s index=%d\n", propname, rc);
  3275. end:
  3276. kfree(val);
  3277. return rc;
  3278. }
  3279. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3280. const char *propname)
  3281. {
  3282. if (display->fw)
  3283. return dsi_parser_count_u32_elems(display->parser_node,
  3284. propname);
  3285. else
  3286. return of_property_count_u32_elems(display->panel_node,
  3287. propname);
  3288. }
  3289. static int dsi_display_parse_dt(struct dsi_display *display)
  3290. {
  3291. int i, rc = 0;
  3292. u32 phy_count = 0;
  3293. struct device_node *of_node = display->pdev->dev.of_node;
  3294. char *dsi_ctrl_name, *dsi_phy_name;
  3295. if (!strcmp(display->display_type, "primary")) {
  3296. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3297. dsi_phy_name = "qcom,dsi-phy-num";
  3298. } else {
  3299. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3300. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3301. }
  3302. display->ctrl_count = dsi_display_get_phandle_count(display,
  3303. dsi_ctrl_name);
  3304. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3305. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3306. display->ctrl_count, phy_count);
  3307. if (!phy_count || !display->ctrl_count) {
  3308. DSI_ERR("no ctrl/phys found\n");
  3309. rc = -ENODEV;
  3310. goto error;
  3311. }
  3312. if (phy_count != display->ctrl_count) {
  3313. DSI_ERR("different ctrl and phy counts\n");
  3314. rc = -ENODEV;
  3315. goto error;
  3316. }
  3317. display_for_each_ctrl(i, display) {
  3318. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3319. int index;
  3320. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3321. display->ctrl_count, i);
  3322. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3323. "qcom,dsi-ctrl", index);
  3324. of_node_put(ctrl->ctrl_of_node);
  3325. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3326. display->ctrl_count, i);
  3327. ctrl->phy_of_node = of_parse_phandle(of_node,
  3328. "qcom,dsi-phy", index);
  3329. of_node_put(ctrl->phy_of_node);
  3330. }
  3331. /* Parse TE data */
  3332. dsi_display_parse_te_data(display);
  3333. /* Parse all external bridges from port 0 */
  3334. display_for_each_ctrl(i, display) {
  3335. display->ext_bridge[i].node_of =
  3336. of_graph_get_remote_node(of_node, 0, i);
  3337. if (display->ext_bridge[i].node_of)
  3338. display->ext_bridge_cnt++;
  3339. else
  3340. break;
  3341. }
  3342. DSI_DEBUG("success\n");
  3343. error:
  3344. return rc;
  3345. }
  3346. static int dsi_display_res_init(struct dsi_display *display)
  3347. {
  3348. int rc = 0;
  3349. int i;
  3350. struct dsi_display_ctrl *ctrl;
  3351. display_for_each_ctrl(i, display) {
  3352. ctrl = &display->ctrl[i];
  3353. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3354. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3355. rc = PTR_ERR(ctrl->ctrl);
  3356. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3357. ctrl->ctrl = NULL;
  3358. goto error_ctrl_put;
  3359. }
  3360. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3361. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3362. rc = PTR_ERR(ctrl->phy);
  3363. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3364. dsi_ctrl_put(ctrl->ctrl);
  3365. ctrl->phy = NULL;
  3366. goto error_ctrl_put;
  3367. }
  3368. }
  3369. display->panel = dsi_panel_get(&display->pdev->dev,
  3370. display->panel_node,
  3371. display->parser_node,
  3372. display->display_type,
  3373. display->cmdline_topology,
  3374. display->trusted_vm_env);
  3375. if (IS_ERR_OR_NULL(display->panel)) {
  3376. rc = PTR_ERR(display->panel);
  3377. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3378. display->panel = NULL;
  3379. goto error_ctrl_put;
  3380. }
  3381. display_for_each_ctrl(i, display) {
  3382. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3383. phy->cfg.force_clk_lane_hs =
  3384. display->panel->host_config.force_hs_clk_lane;
  3385. phy->cfg.phy_type =
  3386. display->panel->host_config.phy_type;
  3387. }
  3388. rc = dsi_display_parse_lane_map(display);
  3389. if (rc) {
  3390. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3391. goto error_ctrl_put;
  3392. }
  3393. rc = dsi_display_clocks_init(display);
  3394. if (rc) {
  3395. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3396. goto error_ctrl_put;
  3397. }
  3398. /**
  3399. * In trusted vm, the connectors will not be enabled
  3400. * until the HW resources are assigned and accepted.
  3401. */
  3402. if (display->trusted_vm_env)
  3403. display->is_active = false;
  3404. else
  3405. display->is_active = true;
  3406. return 0;
  3407. error_ctrl_put:
  3408. for (i = i - 1; i >= 0; i--) {
  3409. ctrl = &display->ctrl[i];
  3410. dsi_ctrl_put(ctrl->ctrl);
  3411. dsi_phy_put(ctrl->phy);
  3412. }
  3413. return rc;
  3414. }
  3415. static int dsi_display_res_deinit(struct dsi_display *display)
  3416. {
  3417. int rc = 0;
  3418. int i;
  3419. struct dsi_display_ctrl *ctrl;
  3420. rc = dsi_display_clocks_deinit(display);
  3421. if (rc)
  3422. DSI_ERR("clocks deinit failed, rc=%d\n", rc);
  3423. display_for_each_ctrl(i, display) {
  3424. ctrl = &display->ctrl[i];
  3425. dsi_phy_put(ctrl->phy);
  3426. dsi_ctrl_put(ctrl->ctrl);
  3427. }
  3428. if (display->panel)
  3429. dsi_panel_put(display->panel);
  3430. return rc;
  3431. }
  3432. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3433. struct dsi_display_mode *mode,
  3434. u32 flags)
  3435. {
  3436. int rc = 0;
  3437. int i;
  3438. struct dsi_display_ctrl *ctrl;
  3439. /*
  3440. * To set a mode:
  3441. * 1. Controllers should be turned off.
  3442. * 2. Link clocks should be off.
  3443. * 3. Phy should be disabled.
  3444. */
  3445. display_for_each_ctrl(i, display) {
  3446. ctrl = &display->ctrl[i];
  3447. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3448. (ctrl->phy_enabled)) {
  3449. rc = -EINVAL;
  3450. goto error;
  3451. }
  3452. }
  3453. error:
  3454. return rc;
  3455. }
  3456. static bool dsi_display_is_seamless_dfps_possible(
  3457. const struct dsi_display *display,
  3458. const struct dsi_display_mode *tgt,
  3459. const enum dsi_dfps_type dfps_type)
  3460. {
  3461. struct dsi_display_mode *cur;
  3462. if (!display || !tgt || !display->panel) {
  3463. DSI_ERR("Invalid params\n");
  3464. return false;
  3465. }
  3466. cur = display->panel->cur_mode;
  3467. if (cur->timing.h_active != tgt->timing.h_active) {
  3468. DSI_DEBUG("timing.h_active differs %d %d\n",
  3469. cur->timing.h_active, tgt->timing.h_active);
  3470. return false;
  3471. }
  3472. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3473. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3474. cur->timing.h_back_porch,
  3475. tgt->timing.h_back_porch);
  3476. return false;
  3477. }
  3478. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3479. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3480. cur->timing.h_sync_width,
  3481. tgt->timing.h_sync_width);
  3482. return false;
  3483. }
  3484. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3485. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3486. cur->timing.h_front_porch,
  3487. tgt->timing.h_front_porch);
  3488. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3489. return false;
  3490. }
  3491. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3492. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3493. cur->timing.h_skew,
  3494. tgt->timing.h_skew);
  3495. return false;
  3496. }
  3497. /* skip polarity comparison */
  3498. if (cur->timing.v_active != tgt->timing.v_active) {
  3499. DSI_DEBUG("timing.v_active differs %d %d\n",
  3500. cur->timing.v_active,
  3501. tgt->timing.v_active);
  3502. return false;
  3503. }
  3504. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3505. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3506. cur->timing.v_back_porch,
  3507. tgt->timing.v_back_porch);
  3508. return false;
  3509. }
  3510. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3511. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3512. cur->timing.v_sync_width,
  3513. tgt->timing.v_sync_width);
  3514. return false;
  3515. }
  3516. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3517. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3518. cur->timing.v_front_porch,
  3519. tgt->timing.v_front_porch);
  3520. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3521. return false;
  3522. }
  3523. /* skip polarity comparison */
  3524. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3525. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3526. cur->timing.refresh_rate,
  3527. tgt->timing.refresh_rate);
  3528. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3529. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3530. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3531. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3532. DSI_DEBUG("flags differs %d %d\n",
  3533. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3534. return true;
  3535. }
  3536. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3537. {
  3538. struct dsi_host_common_cfg *config;
  3539. struct dsi_display_ctrl *m_ctrl;
  3540. int phy_ver;
  3541. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3542. config = &display->panel->host_config;
  3543. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3544. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3545. config->byte_intf_clk_div = 1;
  3546. else
  3547. config->byte_intf_clk_div = 2;
  3548. }
  3549. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3550. u32 bit_clk_rate)
  3551. {
  3552. int rc = 0;
  3553. int i;
  3554. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3555. if (!display->panel) {
  3556. DSI_ERR("Invalid params\n");
  3557. return -EINVAL;
  3558. }
  3559. if (bit_clk_rate == 0) {
  3560. DSI_ERR("Invalid bit clock rate\n");
  3561. return -EINVAL;
  3562. }
  3563. display->config.bit_clk_rate_hz = bit_clk_rate;
  3564. display_for_each_ctrl(i, display) {
  3565. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3566. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3567. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3568. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3569. byte_intf_clk_rate;
  3570. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3571. struct dsi_host_common_cfg *host_cfg;
  3572. mutex_lock(&ctrl->ctrl_lock);
  3573. host_cfg = &display->panel->host_config;
  3574. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3575. num_of_lanes++;
  3576. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3577. num_of_lanes++;
  3578. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3579. num_of_lanes++;
  3580. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3581. num_of_lanes++;
  3582. if (num_of_lanes == 0) {
  3583. DSI_ERR("Invalid lane count\n");
  3584. rc = -EINVAL;
  3585. goto error;
  3586. }
  3587. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3588. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3589. bit_rate_per_lane = bit_rate;
  3590. do_div(bit_rate_per_lane, num_of_lanes);
  3591. pclk_rate = bit_rate;
  3592. do_div(pclk_rate, bpp);
  3593. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3594. bit_rate_per_lane = bit_rate;
  3595. do_div(bit_rate_per_lane, num_of_lanes);
  3596. byte_clk_rate = bit_rate_per_lane;
  3597. do_div(byte_clk_rate, 8);
  3598. byte_intf_clk_rate = byte_clk_rate;
  3599. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3600. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3601. } else {
  3602. do_div(bit_rate, bits_per_symbol);
  3603. bit_rate *= num_of_symbols;
  3604. bit_rate_per_lane = bit_rate;
  3605. do_div(bit_rate_per_lane, num_of_lanes);
  3606. byte_clk_rate = bit_rate_per_lane;
  3607. do_div(byte_clk_rate, 7);
  3608. /* For CPHY, byte_intf_clk is same as byte_clk */
  3609. byte_intf_clk_rate = byte_clk_rate;
  3610. }
  3611. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3612. bit_rate, bit_rate_per_lane);
  3613. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3614. byte_clk_rate, byte_intf_clk_rate);
  3615. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3616. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3617. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3618. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3619. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3620. ctrl->clk_freq, ctrl->cell_index);
  3621. if (rc) {
  3622. DSI_ERR("Failed to update link frequencies\n");
  3623. goto error;
  3624. }
  3625. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3626. error:
  3627. mutex_unlock(&ctrl->ctrl_lock);
  3628. /* TODO: recover ctrl->clk_freq in case of failure */
  3629. if (rc)
  3630. return rc;
  3631. }
  3632. return 0;
  3633. }
  3634. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3635. struct dsi_dyn_clk_delay *delay,
  3636. struct dsi_display_mode *mode)
  3637. {
  3638. u32 esc_clk_rate_hz;
  3639. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3640. u32 hsync_period = 0;
  3641. struct dsi_display_ctrl *m_ctrl;
  3642. struct dsi_ctrl *dsi_ctrl;
  3643. struct dsi_phy_cfg *cfg;
  3644. int phy_ver;
  3645. m_ctrl = &display->ctrl[display->clk_master_idx];
  3646. dsi_ctrl = m_ctrl->ctrl;
  3647. cfg = &(m_ctrl->phy->cfg);
  3648. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3649. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3650. esc_clk_rate_hz);
  3651. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3652. esc_clk_rate_hz);
  3653. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3654. esc_clk_rate_hz);
  3655. hsync_period = dsi_h_total_dce(&mode->timing);
  3656. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3657. if (!display->panel->video_config.eof_bllp_lp11_en)
  3658. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3659. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3660. (display->config.common_config.t_clk_post + 1)) /
  3661. byte_to_esc_ratio) +
  3662. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3663. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3664. ((cfg->timing.lane_v3[3] * 4) +
  3665. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3666. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3667. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3668. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3669. hr_bit_to_esc_ratio);
  3670. delay->pipe_delay2 = 0;
  3671. if (display->panel->host_config.force_hs_clk_lane)
  3672. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3673. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3674. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3675. hr_bit_to_esc_ratio);
  3676. /*
  3677. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3678. * 25us pll delay recommended for phy ver 4.0
  3679. */
  3680. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3681. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3682. delay->pll_delay = 100;
  3683. else
  3684. delay->pll_delay = 25;
  3685. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3686. }
  3687. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3688. struct link_clk_freq *bkp_freq)
  3689. {
  3690. int rc = 0, i;
  3691. u8 ctrl_version;
  3692. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3693. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3694. m_ctrl = &display->ctrl[display->clk_master_idx];
  3695. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3696. ctrl_version = m_ctrl->ctrl->version;
  3697. dsi_clk_prepare_enable(&display->clock_info.src_clks);
  3698. rc = dsi_clk_update_parent(&display->clock_info.shadow_clks,
  3699. &display->clock_info.mux_clks);
  3700. if (rc) {
  3701. DSI_ERR("failed update mux parent to shadow\n");
  3702. goto exit;
  3703. }
  3704. display_for_each_ctrl(i, display) {
  3705. ctrl = &display->ctrl[i];
  3706. if (!ctrl->ctrl)
  3707. continue;
  3708. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3709. ctrl->ctrl->clk_freq.byte_clk_rate,
  3710. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3711. if (rc) {
  3712. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3713. goto recover_byte_clk;
  3714. }
  3715. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3716. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3717. if (rc) {
  3718. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3719. goto recover_pix_clk;
  3720. }
  3721. }
  3722. display_for_each_ctrl(i, display) {
  3723. ctrl = &display->ctrl[i];
  3724. if (ctrl == m_ctrl)
  3725. continue;
  3726. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3727. }
  3728. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3729. /*
  3730. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3731. * and with constant fps, as dynamic refresh will applied with
  3732. * next mdp intf ctrl flush.
  3733. */
  3734. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3735. (dyn_clk_caps->maintain_const_fps))
  3736. goto defer_dfps_wait;
  3737. /* wait for dynamic refresh done */
  3738. display_for_each_ctrl(i, display) {
  3739. ctrl = &display->ctrl[i];
  3740. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3741. if (rc) {
  3742. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3743. goto recover_pix_clk;
  3744. } else {
  3745. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3746. i ? "slave" : "master");
  3747. }
  3748. }
  3749. display_for_each_ctrl(i, display) {
  3750. ctrl = &display->ctrl[i];
  3751. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3752. }
  3753. defer_dfps_wait:
  3754. rc = dsi_clk_update_parent(&display->clock_info.src_clks,
  3755. &display->clock_info.mux_clks);
  3756. if (rc)
  3757. DSI_ERR("could not switch back to src clks %d\n", rc);
  3758. dsi_clk_disable_unprepare(&display->clock_info.src_clks);
  3759. return rc;
  3760. recover_pix_clk:
  3761. display_for_each_ctrl(i, display) {
  3762. ctrl = &display->ctrl[i];
  3763. if (!ctrl->ctrl)
  3764. continue;
  3765. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3766. bkp_freq->pix_clk_rate, i);
  3767. }
  3768. recover_byte_clk:
  3769. display_for_each_ctrl(i, display) {
  3770. ctrl = &display->ctrl[i];
  3771. if (!ctrl->ctrl)
  3772. continue;
  3773. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3774. bkp_freq->byte_clk_rate,
  3775. bkp_freq->byte_intf_clk_rate, i);
  3776. }
  3777. exit:
  3778. dsi_clk_disable_unprepare(&display->clock_info.src_clks);
  3779. return rc;
  3780. }
  3781. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3782. struct dsi_display_mode *mode)
  3783. {
  3784. int rc = 0, mask, i;
  3785. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3786. struct dsi_dyn_clk_delay delay;
  3787. struct link_clk_freq bkp_freq;
  3788. dsi_panel_acquire_panel_lock(display->panel);
  3789. m_ctrl = &display->ctrl[display->clk_master_idx];
  3790. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3791. /* mask PLL unlock, FIFO overflow and underflow errors */
  3792. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3793. BIT(DSI_FIFO_OVERFLOW);
  3794. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3795. /* update the phy timings based on new mode */
  3796. display_for_each_ctrl(i, display) {
  3797. ctrl = &display->ctrl[i];
  3798. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3799. }
  3800. /* back up existing rates to handle failure case */
  3801. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3802. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3803. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3804. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3805. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3806. if (rc) {
  3807. DSI_ERR("failed set link frequencies %d\n", rc);
  3808. goto exit;
  3809. }
  3810. /* calculate pipe delays */
  3811. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3812. /* configure dynamic refresh ctrl registers */
  3813. display_for_each_ctrl(i, display) {
  3814. ctrl = &display->ctrl[i];
  3815. if (!ctrl->phy)
  3816. continue;
  3817. if (ctrl == m_ctrl)
  3818. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3819. else
  3820. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3821. false);
  3822. }
  3823. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3824. exit:
  3825. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3826. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3827. DSI_CLK_OFF);
  3828. /* store newly calculated phy timings in mode private info */
  3829. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3830. mode->priv_info->phy_timing_val,
  3831. mode->priv_info->phy_timing_len);
  3832. dsi_panel_release_panel_lock(display->panel);
  3833. return rc;
  3834. }
  3835. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3836. int clk_rate)
  3837. {
  3838. int rc = 0;
  3839. if (clk_rate <= 0) {
  3840. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3841. return -EINVAL;
  3842. }
  3843. if (clk_rate == display->cached_clk_rate) {
  3844. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  3845. return rc;
  3846. }
  3847. display->cached_clk_rate = clk_rate;
  3848. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  3849. if (!rc) {
  3850. DSI_INFO("%s: bit clk is ready to be configured to '%d'\n",
  3851. __func__, clk_rate);
  3852. atomic_set(&display->clkrate_change_pending, 1);
  3853. } else {
  3854. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  3855. __func__, clk_rate, rc);
  3856. /* Caching clock failed, so don't go on doing so. */
  3857. atomic_set(&display->clkrate_change_pending, 0);
  3858. display->cached_clk_rate = 0;
  3859. }
  3860. return rc;
  3861. }
  3862. static int dsi_display_dfps_update(struct dsi_display *display,
  3863. struct dsi_display_mode *dsi_mode)
  3864. {
  3865. struct dsi_mode_info *timing;
  3866. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3867. struct dsi_display_mode *panel_mode;
  3868. struct dsi_dfps_capabilities dfps_caps;
  3869. int rc = 0;
  3870. int i = 0;
  3871. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3872. if (!display || !dsi_mode || !display->panel) {
  3873. DSI_ERR("Invalid params\n");
  3874. return -EINVAL;
  3875. }
  3876. timing = &dsi_mode->timing;
  3877. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3878. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3879. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  3880. DSI_ERR("dfps or constant fps not supported\n");
  3881. return -ENOTSUPP;
  3882. }
  3883. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  3884. DSI_ERR("dfps clock method not supported\n");
  3885. return -ENOTSUPP;
  3886. }
  3887. /* For split DSI, update the clock master first */
  3888. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  3889. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  3890. m_ctrl = &display->ctrl[display->clk_master_idx];
  3891. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  3892. if (rc) {
  3893. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3894. display->name, i, rc);
  3895. goto error;
  3896. }
  3897. /* Update the rest of the controllers */
  3898. display_for_each_ctrl(i, display) {
  3899. ctrl = &display->ctrl[i];
  3900. if (!ctrl->ctrl || (ctrl == m_ctrl))
  3901. continue;
  3902. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  3903. if (rc) {
  3904. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3905. display->name, i, rc);
  3906. goto error;
  3907. }
  3908. }
  3909. panel_mode = display->panel->cur_mode;
  3910. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  3911. /*
  3912. * dsi_mode_flags flags are used to communicate with other drm driver
  3913. * components, and are transient. They aren't inherently part of the
  3914. * display panel's mode and shouldn't be saved into the cached currently
  3915. * active mode.
  3916. */
  3917. panel_mode->dsi_mode_flags = 0;
  3918. error:
  3919. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  3920. return rc;
  3921. }
  3922. static int dsi_display_dfps_calc_front_porch(
  3923. u32 old_fps,
  3924. u32 new_fps,
  3925. u32 a_total,
  3926. u32 b_total,
  3927. u32 b_fp,
  3928. u32 *b_fp_out)
  3929. {
  3930. s32 b_fp_new;
  3931. int add_porches, diff;
  3932. if (!b_fp_out) {
  3933. DSI_ERR("Invalid params\n");
  3934. return -EINVAL;
  3935. }
  3936. if (!a_total || !new_fps) {
  3937. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  3938. return -EINVAL;
  3939. }
  3940. /*
  3941. * Keep clock, other porches constant, use new fps, calc front porch
  3942. * new_vtotal = old_vtotal * (old_fps / new_fps )
  3943. * new_vfp - old_vfp = new_vtotal - old_vtotal
  3944. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  3945. */
  3946. diff = abs(old_fps - new_fps);
  3947. add_porches = mult_frac(b_total, diff, new_fps);
  3948. if (old_fps > new_fps)
  3949. b_fp_new = b_fp + add_porches;
  3950. else
  3951. b_fp_new = b_fp - add_porches;
  3952. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  3953. new_fps, a_total, b_total, b_fp, b_fp_new);
  3954. if (b_fp_new < 0) {
  3955. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  3956. return -EINVAL;
  3957. }
  3958. /**
  3959. * TODO: To differentiate from clock method when communicating to the
  3960. * other components, perhaps we should set clk here to original value
  3961. */
  3962. *b_fp_out = b_fp_new;
  3963. return 0;
  3964. }
  3965. /**
  3966. * dsi_display_get_dfps_timing() - Get the new dfps values.
  3967. * @display: DSI display handle.
  3968. * @adj_mode: Mode value structure to be changed.
  3969. * It contains old timing values and latest fps value.
  3970. * New timing values are updated based on new fps.
  3971. * @curr_refresh_rate: Current fps rate.
  3972. * If zero , current fps rate is taken from
  3973. * display->panel->cur_mode.
  3974. * Return: error code.
  3975. */
  3976. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  3977. struct dsi_display_mode *adj_mode,
  3978. u32 curr_refresh_rate)
  3979. {
  3980. struct dsi_dfps_capabilities dfps_caps;
  3981. struct dsi_display_mode per_ctrl_mode;
  3982. struct dsi_mode_info *timing;
  3983. struct dsi_ctrl *m_ctrl;
  3984. int rc = 0;
  3985. if (!display || !adj_mode) {
  3986. DSI_ERR("Invalid params\n");
  3987. return -EINVAL;
  3988. }
  3989. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  3990. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3991. if (!dfps_caps.dfps_support) {
  3992. DSI_ERR("dfps not supported by panel\n");
  3993. return -EINVAL;
  3994. }
  3995. per_ctrl_mode = *adj_mode;
  3996. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  3997. if (!curr_refresh_rate) {
  3998. if (!dsi_display_is_seamless_dfps_possible(display,
  3999. &per_ctrl_mode, dfps_caps.type)) {
  4000. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4001. return -EINVAL;
  4002. }
  4003. if (display->panel->cur_mode) {
  4004. curr_refresh_rate =
  4005. display->panel->cur_mode->timing.refresh_rate;
  4006. } else {
  4007. DSI_ERR("cur_mode is not initialized\n");
  4008. return -EINVAL;
  4009. }
  4010. }
  4011. /* TODO: Remove this direct reference to the dsi_ctrl */
  4012. timing = &per_ctrl_mode.timing;
  4013. switch (dfps_caps.type) {
  4014. case DSI_DFPS_IMMEDIATE_VFP:
  4015. rc = dsi_display_dfps_calc_front_porch(
  4016. curr_refresh_rate,
  4017. timing->refresh_rate,
  4018. dsi_h_total_dce(timing),
  4019. DSI_V_TOTAL(timing),
  4020. timing->v_front_porch,
  4021. &adj_mode->timing.v_front_porch);
  4022. break;
  4023. case DSI_DFPS_IMMEDIATE_HFP:
  4024. rc = dsi_display_dfps_calc_front_porch(
  4025. curr_refresh_rate,
  4026. timing->refresh_rate,
  4027. DSI_V_TOTAL(timing),
  4028. dsi_h_total_dce(timing),
  4029. timing->h_front_porch,
  4030. &adj_mode->timing.h_front_porch);
  4031. if (!rc)
  4032. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4033. break;
  4034. default:
  4035. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4036. rc = -ENOTSUPP;
  4037. }
  4038. return rc;
  4039. }
  4040. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4041. struct dsi_display_mode *adj_mode)
  4042. {
  4043. int rc = 0;
  4044. if (!display || !adj_mode) {
  4045. DSI_ERR("Invalid params\n");
  4046. return false;
  4047. }
  4048. /* Currently the only seamless transition is dynamic fps */
  4049. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4050. if (rc) {
  4051. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4052. } else {
  4053. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4054. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4055. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4056. }
  4057. return rc;
  4058. }
  4059. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4060. struct dsi_display_mode *to_mode)
  4061. {
  4062. u32 cur_fps, to_fps;
  4063. u32 cur_h_active, to_h_active;
  4064. u32 cur_v_active, to_v_active;
  4065. cur_fps = cur_mode->timing.refresh_rate;
  4066. to_fps = to_mode->timing.refresh_rate;
  4067. cur_h_active = cur_mode->timing.h_active;
  4068. cur_v_active = cur_mode->timing.v_active;
  4069. to_h_active = to_mode->timing.h_active;
  4070. to_v_active = to_mode->timing.v_active;
  4071. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4072. (cur_fps != to_fps)) {
  4073. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4074. DSI_DEBUG("DMS Modeset with FPS change\n");
  4075. } else {
  4076. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4077. }
  4078. }
  4079. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4080. struct dsi_display_mode *mode,
  4081. u32 flags)
  4082. {
  4083. int rc = 0, clk_rate = 0;
  4084. int i;
  4085. struct dsi_display_ctrl *ctrl;
  4086. struct dsi_display_ctrl *mctrl;
  4087. struct dsi_display_mode_priv_info *priv_info;
  4088. bool commit_phy_timing = false;
  4089. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4090. priv_info = mode->priv_info;
  4091. if (!priv_info) {
  4092. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4093. display->name);
  4094. return -EINVAL;
  4095. }
  4096. SDE_EVT32(mode->dsi_mode_flags);
  4097. if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) {
  4098. display->config.panel_mode = mode->panel_mode;
  4099. display->panel->panel_mode = mode->panel_mode;
  4100. }
  4101. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4102. mode,
  4103. &display->config);
  4104. if (rc) {
  4105. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4106. display->name, rc);
  4107. goto error;
  4108. }
  4109. memcpy(&display->config.lane_map, &display->lane_map,
  4110. sizeof(display->lane_map));
  4111. mctrl = &display->ctrl[display->clk_master_idx];
  4112. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4113. if (mode->dsi_mode_flags &
  4114. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4115. display_for_each_ctrl(i, display) {
  4116. ctrl = &display->ctrl[i];
  4117. if (!ctrl->ctrl || (ctrl != mctrl))
  4118. continue;
  4119. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4120. true);
  4121. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4122. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4123. (dyn_clk_caps->maintain_const_fps)) {
  4124. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4125. true);
  4126. }
  4127. }
  4128. rc = dsi_display_dfps_update(display, mode);
  4129. if (rc) {
  4130. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4131. display->name, rc);
  4132. goto error;
  4133. }
  4134. display_for_each_ctrl(i, display) {
  4135. ctrl = &display->ctrl[i];
  4136. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4137. &display->config, mode, mode->dsi_mode_flags,
  4138. display->dsi_clk_handle);
  4139. if (rc) {
  4140. DSI_ERR("failed to update ctrl config\n");
  4141. goto error;
  4142. }
  4143. }
  4144. if (priv_info->phy_timing_len) {
  4145. display_for_each_ctrl(i, display) {
  4146. ctrl = &display->ctrl[i];
  4147. rc = dsi_phy_set_timing_params(ctrl->phy,
  4148. priv_info->phy_timing_val,
  4149. priv_info->phy_timing_len,
  4150. commit_phy_timing);
  4151. if (rc)
  4152. DSI_ERR("Fail to add timing params\n");
  4153. }
  4154. }
  4155. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4156. return rc;
  4157. }
  4158. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4159. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4160. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4161. if (rc)
  4162. DSI_ERR("dynamic clk change failed %d\n", rc);
  4163. /*
  4164. * skip rest of the opearations since
  4165. * dsi_display_dynamic_clk_switch_vid() already takes
  4166. * care of them.
  4167. */
  4168. return rc;
  4169. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4170. clk_rate = mode->timing.clk_rate_hz;
  4171. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4172. clk_rate);
  4173. if (rc) {
  4174. DSI_ERR("Failed to configure dynamic clk\n");
  4175. return rc;
  4176. }
  4177. }
  4178. }
  4179. display_for_each_ctrl(i, display) {
  4180. ctrl = &display->ctrl[i];
  4181. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4182. mode, mode->dsi_mode_flags,
  4183. display->dsi_clk_handle);
  4184. if (rc) {
  4185. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4186. display->name, rc);
  4187. goto error;
  4188. }
  4189. }
  4190. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4191. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4192. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4193. u64 to_bitclk = mode->timing.clk_rate_hz;
  4194. commit_phy_timing = true;
  4195. /* No need to set clkrate pending flag if clocks are same */
  4196. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4197. atomic_set(&display->clkrate_change_pending, 1);
  4198. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4199. }
  4200. if (priv_info->phy_timing_len) {
  4201. display_for_each_ctrl(i, display) {
  4202. ctrl = &display->ctrl[i];
  4203. rc = dsi_phy_set_timing_params(ctrl->phy,
  4204. priv_info->phy_timing_val,
  4205. priv_info->phy_timing_len,
  4206. commit_phy_timing);
  4207. if (rc)
  4208. DSI_ERR("failed to add DSI PHY timing params\n");
  4209. }
  4210. }
  4211. error:
  4212. return rc;
  4213. }
  4214. /**
  4215. * _dsi_display_dev_init - initializes the display device
  4216. * Initialization will acquire references to the resources required for the
  4217. * display hardware to function.
  4218. * @display: Handle to the display
  4219. * Returns: Zero on success
  4220. */
  4221. static int _dsi_display_dev_init(struct dsi_display *display)
  4222. {
  4223. int rc = 0;
  4224. if (!display) {
  4225. DSI_ERR("invalid display\n");
  4226. return -EINVAL;
  4227. }
  4228. if (!display->panel_node)
  4229. return 0;
  4230. mutex_lock(&display->display_lock);
  4231. display->parser = dsi_parser_get(&display->pdev->dev);
  4232. if (display->fw && display->parser)
  4233. display->parser_node = dsi_parser_get_head_node(
  4234. display->parser, display->fw->data,
  4235. display->fw->size);
  4236. rc = dsi_display_parse_dt(display);
  4237. if (rc) {
  4238. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4239. goto error;
  4240. }
  4241. rc = dsi_display_res_init(display);
  4242. if (rc) {
  4243. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4244. display->name, rc);
  4245. goto error;
  4246. }
  4247. error:
  4248. mutex_unlock(&display->display_lock);
  4249. return rc;
  4250. }
  4251. /**
  4252. * _dsi_display_dev_deinit - deinitializes the display device
  4253. * All the resources acquired during device init will be released.
  4254. * @display: Handle to the display
  4255. * Returns: Zero on success
  4256. */
  4257. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4258. {
  4259. int rc = 0;
  4260. if (!display) {
  4261. DSI_ERR("invalid display\n");
  4262. return -EINVAL;
  4263. }
  4264. mutex_lock(&display->display_lock);
  4265. rc = dsi_display_res_deinit(display);
  4266. if (rc)
  4267. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4268. display->name, rc);
  4269. mutex_unlock(&display->display_lock);
  4270. return rc;
  4271. }
  4272. /**
  4273. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4274. * @dsi_display: Pointer to dsi display
  4275. * Returns: Zero on success
  4276. */
  4277. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4278. {
  4279. struct dsi_display *display = dsi_display;
  4280. int rc = 0;
  4281. /* Remove the panel vote that was added during dsi display probe */
  4282. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4283. if (rc)
  4284. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4285. display->panel->name, rc);
  4286. return rc;
  4287. }
  4288. /**
  4289. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4290. * @dsi_display: Pointer to dsi display
  4291. * Returns: Zero on success
  4292. */
  4293. int dsi_display_cont_splash_config(void *dsi_display)
  4294. {
  4295. struct dsi_display *display = dsi_display;
  4296. int rc = 0;
  4297. /* Vote for gdsc required to read register address space */
  4298. if (!display) {
  4299. DSI_ERR("invalid input display param\n");
  4300. return -EINVAL;
  4301. }
  4302. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4303. if (rc < 0) {
  4304. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4305. rc);
  4306. return rc;
  4307. }
  4308. mutex_lock(&display->display_lock);
  4309. display->is_cont_splash_enabled = true;
  4310. /* Update splash status for clock manager */
  4311. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4312. display->is_cont_splash_enabled);
  4313. /* Set up ctrl isr before enabling core clk */
  4314. dsi_display_ctrl_isr_configure(display, true);
  4315. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4316. * regulator are inplicit from pre clk on callback
  4317. */
  4318. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4319. DSI_ALL_CLKS, DSI_CLK_ON);
  4320. if (rc) {
  4321. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4322. display->name, rc);
  4323. goto clk_manager_update;
  4324. }
  4325. mutex_unlock(&display->display_lock);
  4326. /* Set the current brightness level */
  4327. dsi_panel_bl_handoff(display->panel);
  4328. return rc;
  4329. clk_manager_update:
  4330. dsi_display_ctrl_isr_configure(display, false);
  4331. /* Update splash status for clock manager */
  4332. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4333. false);
  4334. pm_runtime_put_sync(display->drm_dev->dev);
  4335. display->is_cont_splash_enabled = false;
  4336. mutex_unlock(&display->display_lock);
  4337. return rc;
  4338. }
  4339. /**
  4340. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4341. * @display: Pointer to dsi display
  4342. * Returns: Zero on success
  4343. */
  4344. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4345. {
  4346. int rc = 0;
  4347. if (!display->is_cont_splash_enabled)
  4348. return 0;
  4349. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4350. DSI_ALL_CLKS, DSI_CLK_OFF);
  4351. if (rc)
  4352. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4353. display->name, rc);
  4354. pm_runtime_put_sync(display->drm_dev->dev);
  4355. display->is_cont_splash_enabled = false;
  4356. /* Update splash status for clock manager */
  4357. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4358. display->is_cont_splash_enabled);
  4359. return rc;
  4360. }
  4361. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4362. {
  4363. int rc = 0;
  4364. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4365. if (!rc) {
  4366. DSI_INFO("dsi bit clk has been configured to %d\n",
  4367. display->cached_clk_rate);
  4368. atomic_set(&display->clkrate_change_pending, 0);
  4369. } else {
  4370. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4371. display->cached_clk_rate, rc);
  4372. }
  4373. return rc;
  4374. }
  4375. static int dsi_display_validate_split_link(struct dsi_display *display)
  4376. {
  4377. int i, rc = 0;
  4378. struct dsi_display_ctrl *ctrl;
  4379. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4380. if (!host->split_link.split_link_enabled)
  4381. return 0;
  4382. if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4383. DSI_ERR("[%s] split link is not supported in command mode\n",
  4384. display->name);
  4385. rc = -ENOTSUPP;
  4386. goto error;
  4387. }
  4388. display_for_each_ctrl(i, display) {
  4389. ctrl = &display->ctrl[i];
  4390. if (!ctrl->ctrl->split_link_supported) {
  4391. DSI_ERR("[%s] split link is not supported by hw\n",
  4392. display->name);
  4393. rc = -ENOTSUPP;
  4394. goto error;
  4395. }
  4396. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4397. }
  4398. DSI_DEBUG("Split link is enabled\n");
  4399. return 0;
  4400. error:
  4401. host->split_link.split_link_enabled = false;
  4402. return rc;
  4403. }
  4404. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4405. {
  4406. int rc = 0;
  4407. struct dsi_display *display;
  4408. if (!data)
  4409. return -EINVAL;
  4410. rc = dsi_ctrl_get_io_resources(io_res);
  4411. if (rc)
  4412. goto end;
  4413. rc = dsi_phy_get_io_resources(io_res);
  4414. if (rc)
  4415. goto end;
  4416. display = (struct dsi_display *)data;
  4417. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4418. end:
  4419. return rc;
  4420. }
  4421. static int dsi_display_pre_release(void *data)
  4422. {
  4423. if (!data)
  4424. return -EINVAL;
  4425. dsi_display_ctrl_irq_update((struct dsi_display *)data, false);
  4426. return 0;
  4427. }
  4428. static int dsi_display_pre_acquire(void *data)
  4429. {
  4430. if (!data)
  4431. return -EINVAL;
  4432. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4433. return 0;
  4434. }
  4435. /**
  4436. * dsi_display_bind - bind dsi device with controlling device
  4437. * @dev: Pointer to base of platform device
  4438. * @master: Pointer to container of drm device
  4439. * @data: Pointer to private data
  4440. * Returns: Zero on success
  4441. */
  4442. static int dsi_display_bind(struct device *dev,
  4443. struct device *master,
  4444. void *data)
  4445. {
  4446. struct dsi_display_ctrl *display_ctrl;
  4447. struct drm_device *drm;
  4448. struct dsi_display *display;
  4449. struct dsi_clk_info info;
  4450. struct clk_ctrl_cb clk_cb;
  4451. void *handle = NULL;
  4452. struct platform_device *pdev = to_platform_device(dev);
  4453. char *client1 = "dsi_clk_client";
  4454. char *client2 = "mdp_event_client";
  4455. struct msm_vm_ops vm_event_ops = {
  4456. .vm_get_io_resources = dsi_display_get_io_resources,
  4457. .vm_pre_hw_release = dsi_display_pre_release,
  4458. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4459. };
  4460. int i, rc = 0;
  4461. if (!dev || !pdev || !master) {
  4462. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4463. dev, pdev, master);
  4464. return -EINVAL;
  4465. }
  4466. drm = dev_get_drvdata(master);
  4467. display = platform_get_drvdata(pdev);
  4468. if (!drm || !display) {
  4469. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4470. drm, display);
  4471. return -EINVAL;
  4472. }
  4473. if (!display->panel_node)
  4474. return 0;
  4475. if (!display->fw)
  4476. display->name = display->panel_node->name;
  4477. /* defer bind if ext bridge driver is not loaded */
  4478. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4479. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4480. if (!of_drm_find_bridge(
  4481. display->ext_bridge[i].node_of)) {
  4482. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4483. display->ext_bridge[i].node_of->full_name);
  4484. return -EPROBE_DEFER;
  4485. }
  4486. }
  4487. }
  4488. mutex_lock(&display->display_lock);
  4489. rc = dsi_display_validate_split_link(display);
  4490. if (rc) {
  4491. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4492. display->name, rc);
  4493. goto error;
  4494. }
  4495. rc = dsi_display_debugfs_init(display);
  4496. if (rc) {
  4497. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4498. goto error;
  4499. }
  4500. atomic_set(&display->clkrate_change_pending, 0);
  4501. display->cached_clk_rate = 0;
  4502. memset(&info, 0x0, sizeof(info));
  4503. display_for_each_ctrl(i, display) {
  4504. display_ctrl = &display->ctrl[i];
  4505. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4506. if (rc) {
  4507. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4508. display->name, i, rc);
  4509. goto error_ctrl_deinit;
  4510. }
  4511. display_ctrl->ctrl->horiz_index = i;
  4512. rc = dsi_phy_drv_init(display_ctrl->phy);
  4513. if (rc) {
  4514. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4515. display->name, i, rc);
  4516. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4517. goto error_ctrl_deinit;
  4518. }
  4519. display_ctrl->ctrl->dma_cmd_workq = display->dma_cmd_workq;
  4520. memcpy(&info.c_clks[i],
  4521. (&display_ctrl->ctrl->clk_info.core_clks),
  4522. sizeof(struct dsi_core_clk_info));
  4523. memcpy(&info.l_hs_clks[i],
  4524. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4525. sizeof(struct dsi_link_hs_clk_info));
  4526. memcpy(&info.l_lp_clks[i],
  4527. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4528. sizeof(struct dsi_link_lp_clk_info));
  4529. info.c_clks[i].drm = drm;
  4530. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4531. }
  4532. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4533. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4534. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4535. info.post_clkon_cb = dsi_post_clkon_cb;
  4536. info.priv_data = display;
  4537. info.master_ndx = display->clk_master_idx;
  4538. info.dsi_ctrl_count = display->ctrl_count;
  4539. snprintf(info.name, MAX_STRING_LEN,
  4540. "DSI_MNGR-%s", display->name);
  4541. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4542. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4543. rc = PTR_ERR(display->clk_mngr);
  4544. display->clk_mngr = NULL;
  4545. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4546. goto error_ctrl_deinit;
  4547. }
  4548. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4549. if (IS_ERR_OR_NULL(handle)) {
  4550. rc = PTR_ERR(handle);
  4551. DSI_ERR("failed to register %s client, rc = %d\n",
  4552. client1, rc);
  4553. goto error_clk_deinit;
  4554. } else {
  4555. display->dsi_clk_handle = handle;
  4556. }
  4557. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4558. if (IS_ERR_OR_NULL(handle)) {
  4559. rc = PTR_ERR(handle);
  4560. DSI_ERR("failed to register %s client, rc = %d\n",
  4561. client2, rc);
  4562. goto error_clk_client_deinit;
  4563. } else {
  4564. display->mdp_clk_handle = handle;
  4565. }
  4566. clk_cb.priv = display;
  4567. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4568. display_for_each_ctrl(i, display) {
  4569. display_ctrl = &display->ctrl[i];
  4570. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4571. if (rc) {
  4572. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4573. display->name, i, rc);
  4574. goto error_ctrl_deinit;
  4575. }
  4576. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4577. if (rc) {
  4578. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4579. display->name, i, rc);
  4580. goto error_ctrl_deinit;
  4581. }
  4582. }
  4583. dsi_display_update_byte_intf_div(display);
  4584. rc = dsi_display_mipi_host_init(display);
  4585. if (rc) {
  4586. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4587. display->name, rc);
  4588. goto error_ctrl_deinit;
  4589. }
  4590. rc = dsi_panel_drv_init(display->panel, &display->host);
  4591. if (rc) {
  4592. if (rc != -EPROBE_DEFER)
  4593. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4594. display->name, rc);
  4595. goto error_host_deinit;
  4596. }
  4597. DSI_INFO("Successfully bind display panel '%s'\n", display->name);
  4598. display->drm_dev = drm;
  4599. display_for_each_ctrl(i, display) {
  4600. display_ctrl = &display->ctrl[i];
  4601. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4602. continue;
  4603. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4604. &display_ctrl->ctrl->clk_freq);
  4605. if (rc) {
  4606. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4607. display->name, rc);
  4608. goto error;
  4609. }
  4610. }
  4611. /* register te irq handler */
  4612. dsi_display_register_te_irq(display);
  4613. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4614. goto error;
  4615. error_host_deinit:
  4616. (void)dsi_display_mipi_host_deinit(display);
  4617. error_clk_client_deinit:
  4618. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4619. error_clk_deinit:
  4620. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4621. error_ctrl_deinit:
  4622. for (i = i - 1; i >= 0; i--) {
  4623. display_ctrl = &display->ctrl[i];
  4624. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4625. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4626. }
  4627. (void)dsi_display_debugfs_deinit(display);
  4628. error:
  4629. mutex_unlock(&display->display_lock);
  4630. return rc;
  4631. }
  4632. /**
  4633. * dsi_display_unbind - unbind dsi from controlling device
  4634. * @dev: Pointer to base of platform device
  4635. * @master: Pointer to container of drm device
  4636. * @data: Pointer to private data
  4637. */
  4638. static void dsi_display_unbind(struct device *dev,
  4639. struct device *master, void *data)
  4640. {
  4641. struct dsi_display_ctrl *display_ctrl;
  4642. struct dsi_display *display;
  4643. struct platform_device *pdev = to_platform_device(dev);
  4644. int i, rc = 0;
  4645. if (!dev || !pdev || !master) {
  4646. DSI_ERR("invalid param(s)\n");
  4647. return;
  4648. }
  4649. display = platform_get_drvdata(pdev);
  4650. if (!display || !display->panel_node) {
  4651. DSI_ERR("invalid display\n");
  4652. return;
  4653. }
  4654. mutex_lock(&display->display_lock);
  4655. rc = dsi_display_mipi_host_deinit(display);
  4656. if (rc)
  4657. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4658. display->name,
  4659. rc);
  4660. display_for_each_ctrl(i, display) {
  4661. display_ctrl = &display->ctrl[i];
  4662. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4663. if (rc)
  4664. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4665. display->name, i, rc);
  4666. display->ctrl->ctrl->dma_cmd_workq = NULL;
  4667. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4668. if (rc)
  4669. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4670. display->name, i, rc);
  4671. }
  4672. atomic_set(&display->clkrate_change_pending, 0);
  4673. (void)dsi_display_debugfs_deinit(display);
  4674. mutex_unlock(&display->display_lock);
  4675. }
  4676. static const struct component_ops dsi_display_comp_ops = {
  4677. .bind = dsi_display_bind,
  4678. .unbind = dsi_display_unbind,
  4679. };
  4680. static struct platform_driver dsi_display_driver = {
  4681. .probe = dsi_display_dev_probe,
  4682. .remove = dsi_display_dev_remove,
  4683. .driver = {
  4684. .name = "msm-dsi-display",
  4685. .of_match_table = dsi_display_dt_match,
  4686. .suppress_bind_attrs = true,
  4687. },
  4688. };
  4689. static int dsi_display_init(struct dsi_display *display)
  4690. {
  4691. int rc = 0;
  4692. struct platform_device *pdev = display->pdev;
  4693. mutex_init(&display->display_lock);
  4694. rc = _dsi_display_dev_init(display);
  4695. if (rc) {
  4696. DSI_ERR("device init failed, rc=%d\n", rc);
  4697. goto end;
  4698. }
  4699. /*
  4700. * Vote on panel regulator is added to make sure panel regulators
  4701. * are ON for cont-splash enabled usecase.
  4702. * This panel regulator vote will be removed only in:
  4703. * 1) device suspend when cont-splash is enabled.
  4704. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4705. * For GKI, adding this vote will make sure that sync_state
  4706. * kernel driver doesn't disable the panel regulators after
  4707. * dsi probe is complete.
  4708. */
  4709. if (display->panel) {
  4710. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4711. true);
  4712. if (rc) {
  4713. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4714. display->panel->name, rc);
  4715. return rc;
  4716. }
  4717. }
  4718. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4719. if (rc)
  4720. DSI_ERR("component add failed, rc=%d\n", rc);
  4721. DSI_DEBUG("component add success: %s\n", display->name);
  4722. end:
  4723. return rc;
  4724. }
  4725. static void dsi_display_firmware_display(const struct firmware *fw,
  4726. void *context)
  4727. {
  4728. struct dsi_display *display = context;
  4729. if (fw) {
  4730. DSI_DEBUG("reading data from firmware, size=%zd\n",
  4731. fw->size);
  4732. display->fw = fw;
  4733. display->name = "dsi_firmware_display";
  4734. }
  4735. if (dsi_display_init(display))
  4736. return;
  4737. DSI_DEBUG("success\n");
  4738. }
  4739. int dsi_display_dev_probe(struct platform_device *pdev)
  4740. {
  4741. struct dsi_display *display = NULL;
  4742. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4743. int rc = 0, index = DSI_PRIMARY;
  4744. bool firm_req = false;
  4745. struct dsi_display_boot_param *boot_disp;
  4746. if (!pdev || !pdev->dev.of_node) {
  4747. DSI_ERR("pdev not found\n");
  4748. rc = -ENODEV;
  4749. goto end;
  4750. }
  4751. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4752. if (!display) {
  4753. rc = -ENOMEM;
  4754. goto end;
  4755. }
  4756. display->dma_cmd_workq = create_singlethread_workqueue(
  4757. "dsi_dma_cmd_workq");
  4758. if (!display->dma_cmd_workq) {
  4759. DSI_ERR("failed to create work queue\n");
  4760. rc = -EINVAL;
  4761. goto end;
  4762. }
  4763. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  4764. if (!mdp_node) {
  4765. DSI_ERR("mdp_node not found\n");
  4766. rc = -ENODEV;
  4767. goto end;
  4768. }
  4769. display->trusted_vm_env = of_property_read_bool(mdp_node,
  4770. "qcom,sde-trusted-vm-env");
  4771. if (display->trusted_vm_env)
  4772. DSI_INFO("Display enabled with trusted vm path\n");
  4773. /* initialize panel id to UINT64_MAX */
  4774. display->panel_id = ~0x0;
  4775. display->display_type = of_get_property(pdev->dev.of_node,
  4776. "label", NULL);
  4777. if (!display->display_type)
  4778. display->display_type = "primary";
  4779. if (!strcmp(display->display_type, "secondary"))
  4780. index = DSI_SECONDARY;
  4781. boot_disp = &boot_displays[index];
  4782. node = pdev->dev.of_node;
  4783. if (boot_disp->boot_disp_en) {
  4784. /* The panel name should be same as UEFI name index */
  4785. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4786. if (!panel_node)
  4787. DSI_WARN("panel_node %s not found\n", boot_disp->name);
  4788. } else {
  4789. panel_node = of_parse_phandle(node,
  4790. "qcom,dsi-default-panel", 0);
  4791. if (!panel_node)
  4792. DSI_WARN("default panel not found\n");
  4793. if (IS_ENABLED(CONFIG_DSI_PARSER) && !display->trusted_vm_env)
  4794. firm_req = !request_firmware_nowait(
  4795. THIS_MODULE, 1, "dsi_prop",
  4796. &pdev->dev, GFP_KERNEL, display,
  4797. dsi_display_firmware_display);
  4798. }
  4799. boot_disp->node = pdev->dev.of_node;
  4800. boot_disp->disp = display;
  4801. display->panel_node = panel_node;
  4802. display->pdev = pdev;
  4803. display->boot_disp = boot_disp;
  4804. dsi_display_parse_cmdline_topology(display, index);
  4805. platform_set_drvdata(pdev, display);
  4806. /* initialize display in firmware callback */
  4807. if (!firm_req) {
  4808. rc = dsi_display_init(display);
  4809. if (rc)
  4810. goto end;
  4811. }
  4812. return 0;
  4813. end:
  4814. if (display)
  4815. devm_kfree(&pdev->dev, display);
  4816. return rc;
  4817. }
  4818. int dsi_display_dev_remove(struct platform_device *pdev)
  4819. {
  4820. int rc = 0, i = 0;
  4821. struct dsi_display *display;
  4822. struct dsi_display_ctrl *ctrl;
  4823. if (!pdev) {
  4824. DSI_ERR("Invalid device\n");
  4825. return -EINVAL;
  4826. }
  4827. display = platform_get_drvdata(pdev);
  4828. /* decrement ref count */
  4829. of_node_put(display->panel_node);
  4830. if (display->dma_cmd_workq) {
  4831. flush_workqueue(display->dma_cmd_workq);
  4832. destroy_workqueue(display->dma_cmd_workq);
  4833. display->dma_cmd_workq = NULL;
  4834. display_for_each_ctrl(i, display) {
  4835. ctrl = &display->ctrl[i];
  4836. if (!ctrl->ctrl)
  4837. continue;
  4838. ctrl->ctrl->dma_cmd_workq = NULL;
  4839. }
  4840. }
  4841. (void)_dsi_display_dev_deinit(display);
  4842. platform_set_drvdata(pdev, NULL);
  4843. devm_kfree(&pdev->dev, display);
  4844. return rc;
  4845. }
  4846. int dsi_display_get_num_of_displays(void)
  4847. {
  4848. int i, count = 0;
  4849. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  4850. struct dsi_display *display = boot_displays[i].disp;
  4851. if (display && display->panel_node)
  4852. count++;
  4853. }
  4854. return count;
  4855. }
  4856. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  4857. {
  4858. int index = 0, count = 0;
  4859. if (!display_array || !max_display_count) {
  4860. DSI_ERR("invalid params\n");
  4861. return 0;
  4862. }
  4863. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  4864. struct dsi_display *display = boot_displays[index].disp;
  4865. if (display && display->panel_node)
  4866. display_array[count++] = display;
  4867. }
  4868. return count;
  4869. }
  4870. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  4871. {
  4872. if (!display)
  4873. return;
  4874. mutex_lock(&display->display_lock);
  4875. display->is_active = is_active;
  4876. mutex_unlock(&display->display_lock);
  4877. }
  4878. int dsi_display_drm_bridge_init(struct dsi_display *display,
  4879. struct drm_encoder *enc)
  4880. {
  4881. int rc = 0;
  4882. struct dsi_bridge *bridge;
  4883. struct msm_drm_private *priv = NULL;
  4884. if (!display || !display->drm_dev || !enc) {
  4885. DSI_ERR("invalid param(s)\n");
  4886. return -EINVAL;
  4887. }
  4888. mutex_lock(&display->display_lock);
  4889. priv = display->drm_dev->dev_private;
  4890. if (!priv) {
  4891. DSI_ERR("Private data is not present\n");
  4892. rc = -EINVAL;
  4893. goto error;
  4894. }
  4895. if (display->bridge) {
  4896. DSI_ERR("display is already initialize\n");
  4897. goto error;
  4898. }
  4899. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  4900. if (IS_ERR_OR_NULL(bridge)) {
  4901. rc = PTR_ERR(bridge);
  4902. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  4903. goto error;
  4904. }
  4905. display->bridge = bridge;
  4906. priv->bridges[priv->num_bridges++] = &bridge->base;
  4907. error:
  4908. mutex_unlock(&display->display_lock);
  4909. return rc;
  4910. }
  4911. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  4912. {
  4913. int rc = 0;
  4914. if (!display) {
  4915. DSI_ERR("Invalid params\n");
  4916. return -EINVAL;
  4917. }
  4918. mutex_lock(&display->display_lock);
  4919. dsi_drm_bridge_cleanup(display->bridge);
  4920. display->bridge = NULL;
  4921. mutex_unlock(&display->display_lock);
  4922. return rc;
  4923. }
  4924. /* Hook functions to call external connector, pointer validation is
  4925. * done in dsi_display_drm_ext_bridge_init.
  4926. */
  4927. static enum drm_connector_status dsi_display_drm_ext_detect(
  4928. struct drm_connector *connector,
  4929. bool force,
  4930. void *disp)
  4931. {
  4932. struct dsi_display *display = disp;
  4933. return display->ext_conn->funcs->detect(display->ext_conn, force);
  4934. }
  4935. static int dsi_display_drm_ext_get_modes(
  4936. struct drm_connector *connector, void *disp,
  4937. const struct msm_resource_caps_info *avail_res)
  4938. {
  4939. struct dsi_display *display = disp;
  4940. struct drm_display_mode *pmode, *pt;
  4941. int count;
  4942. /* if there are modes defined in panel, ignore external modes */
  4943. if (display->panel->num_timing_nodes)
  4944. return dsi_connector_get_modes(connector, disp, avail_res);
  4945. count = display->ext_conn->helper_private->get_modes(
  4946. display->ext_conn);
  4947. list_for_each_entry_safe(pmode, pt,
  4948. &display->ext_conn->probed_modes, head) {
  4949. list_move_tail(&pmode->head, &connector->probed_modes);
  4950. }
  4951. connector->display_info = display->ext_conn->display_info;
  4952. return count;
  4953. }
  4954. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  4955. struct drm_connector *connector,
  4956. struct drm_display_mode *mode,
  4957. void *disp, const struct msm_resource_caps_info *avail_res)
  4958. {
  4959. struct dsi_display *display = disp;
  4960. enum drm_mode_status status;
  4961. /* always do internal mode_valid check */
  4962. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  4963. if (status != MODE_OK)
  4964. return status;
  4965. return display->ext_conn->helper_private->mode_valid(
  4966. display->ext_conn, mode);
  4967. }
  4968. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  4969. void *disp,
  4970. struct drm_atomic_state *state)
  4971. {
  4972. struct dsi_display *display = disp;
  4973. struct drm_connector_state *c_state;
  4974. c_state = drm_atomic_get_new_connector_state(state, connector);
  4975. return display->ext_conn->helper_private->atomic_check(
  4976. display->ext_conn, state);
  4977. }
  4978. static int dsi_display_ext_get_info(struct drm_connector *connector,
  4979. struct msm_display_info *info, void *disp)
  4980. {
  4981. struct dsi_display *display;
  4982. int i;
  4983. if (!info || !disp) {
  4984. DSI_ERR("invalid params\n");
  4985. return -EINVAL;
  4986. }
  4987. display = disp;
  4988. if (!display->panel) {
  4989. DSI_ERR("invalid display panel\n");
  4990. return -EINVAL;
  4991. }
  4992. mutex_lock(&display->display_lock);
  4993. memset(info, 0, sizeof(struct msm_display_info));
  4994. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  4995. info->num_of_h_tiles = display->ctrl_count;
  4996. for (i = 0; i < info->num_of_h_tiles; i++)
  4997. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  4998. info->is_connected = connector->status != connector_status_disconnected;
  4999. if (!strcmp(display->display_type, "primary"))
  5000. info->display_type = SDE_CONNECTOR_PRIMARY;
  5001. else if (!strcmp(display->display_type, "secondary"))
  5002. info->display_type = SDE_CONNECTOR_SECONDARY;
  5003. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5004. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5005. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5006. mutex_unlock(&display->display_lock);
  5007. return 0;
  5008. }
  5009. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5010. const struct drm_display_mode *drm_mode,
  5011. struct msm_mode_info *mode_info,
  5012. void *display, const struct msm_resource_caps_info *avail_res)
  5013. {
  5014. struct msm_display_topology *topology;
  5015. if (!drm_mode || !mode_info ||
  5016. !avail_res || !avail_res->max_mixer_width)
  5017. return -EINVAL;
  5018. memset(mode_info, 0, sizeof(*mode_info));
  5019. mode_info->frame_rate = drm_mode->vrefresh;
  5020. mode_info->vtotal = drm_mode->vtotal;
  5021. topology = &mode_info->topology;
  5022. topology->num_lm = (avail_res->max_mixer_width
  5023. <= drm_mode->hdisplay) ? 2 : 1;
  5024. topology->num_enc = 0;
  5025. topology->num_intf = topology->num_lm;
  5026. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5027. return 0;
  5028. }
  5029. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5030. struct drm_bridge *bridge)
  5031. {
  5032. struct msm_drm_private *priv;
  5033. struct sde_kms *sde_kms;
  5034. struct drm_connector *conn;
  5035. struct drm_connector_list_iter conn_iter;
  5036. struct sde_connector *sde_conn;
  5037. struct dsi_display *display;
  5038. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5039. int i;
  5040. if (!bridge || !bridge->encoder) {
  5041. SDE_ERROR("invalid argument\n");
  5042. return NULL;
  5043. }
  5044. priv = bridge->dev->dev_private;
  5045. sde_kms = to_sde_kms(priv->kms);
  5046. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5047. drm_for_each_connector_iter(conn, &conn_iter) {
  5048. sde_conn = to_sde_connector(conn);
  5049. if (sde_conn->encoder == bridge->encoder) {
  5050. display = sde_conn->display;
  5051. display_for_each_ctrl(i, display) {
  5052. if (display->ext_bridge[i].bridge == bridge) {
  5053. dsi_bridge = &display->ext_bridge[i];
  5054. break;
  5055. }
  5056. }
  5057. }
  5058. }
  5059. drm_connector_list_iter_end(&conn_iter);
  5060. return dsi_bridge;
  5061. }
  5062. static void dsi_display_drm_ext_adjust_timing(
  5063. const struct dsi_display *display,
  5064. struct drm_display_mode *mode)
  5065. {
  5066. mode->hdisplay /= display->ctrl_count;
  5067. mode->hsync_start /= display->ctrl_count;
  5068. mode->hsync_end /= display->ctrl_count;
  5069. mode->htotal /= display->ctrl_count;
  5070. mode->hskew /= display->ctrl_count;
  5071. mode->clock /= display->ctrl_count;
  5072. }
  5073. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5074. struct drm_bridge *bridge,
  5075. const struct drm_display_mode *mode)
  5076. {
  5077. struct dsi_display_ext_bridge *ext_bridge;
  5078. struct drm_display_mode tmp;
  5079. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5080. if (!ext_bridge)
  5081. return MODE_ERROR;
  5082. tmp = *mode;
  5083. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5084. return ext_bridge->orig_funcs->mode_valid(bridge, &tmp);
  5085. }
  5086. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5087. struct drm_bridge *bridge,
  5088. const struct drm_display_mode *mode,
  5089. struct drm_display_mode *adjusted_mode)
  5090. {
  5091. struct dsi_display_ext_bridge *ext_bridge;
  5092. struct drm_display_mode tmp;
  5093. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5094. if (!ext_bridge)
  5095. return false;
  5096. tmp = *mode;
  5097. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5098. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5099. }
  5100. static void dsi_display_drm_ext_bridge_mode_set(
  5101. struct drm_bridge *bridge,
  5102. const struct drm_display_mode *mode,
  5103. const struct drm_display_mode *adjusted_mode)
  5104. {
  5105. struct dsi_display_ext_bridge *ext_bridge;
  5106. struct drm_display_mode tmp;
  5107. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5108. if (!ext_bridge)
  5109. return;
  5110. tmp = *mode;
  5111. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5112. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5113. }
  5114. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5115. struct mipi_dsi_device *dsi)
  5116. {
  5117. struct dsi_display *display = to_dsi_display(host);
  5118. struct dsi_panel *panel;
  5119. if (!host || !dsi || !display->panel) {
  5120. DSI_ERR("Invalid param\n");
  5121. return -EINVAL;
  5122. }
  5123. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5124. dsi->name, dsi->channel, dsi->lanes,
  5125. dsi->format, dsi->mode_flags);
  5126. panel = display->panel;
  5127. panel->host_config.data_lanes = 0;
  5128. if (dsi->lanes > 0)
  5129. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5130. if (dsi->lanes > 1)
  5131. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5132. if (dsi->lanes > 2)
  5133. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5134. if (dsi->lanes > 3)
  5135. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5136. switch (dsi->format) {
  5137. case MIPI_DSI_FMT_RGB888:
  5138. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5139. break;
  5140. case MIPI_DSI_FMT_RGB666:
  5141. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5142. break;
  5143. case MIPI_DSI_FMT_RGB666_PACKED:
  5144. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5145. break;
  5146. case MIPI_DSI_FMT_RGB565:
  5147. default:
  5148. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5149. break;
  5150. }
  5151. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5152. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5153. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5154. panel->video_config.traffic_mode =
  5155. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5156. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5157. panel->video_config.traffic_mode =
  5158. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5159. else
  5160. panel->video_config.traffic_mode =
  5161. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5162. panel->video_config.hsa_lp11_en =
  5163. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5164. panel->video_config.hbp_lp11_en =
  5165. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5166. panel->video_config.hfp_lp11_en =
  5167. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5168. panel->video_config.pulse_mode_hsa_he =
  5169. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5170. panel->video_config.bllp_lp11_en =
  5171. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BLLP;
  5172. panel->video_config.eof_bllp_lp11_en =
  5173. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_EOF_BLLP;
  5174. } else {
  5175. panel->panel_mode = DSI_OP_CMD_MODE;
  5176. DSI_ERR("command mode not supported by ext bridge\n");
  5177. return -ENOTSUPP;
  5178. }
  5179. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5180. return 0;
  5181. }
  5182. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5183. .attach = dsi_host_ext_attach,
  5184. .detach = dsi_host_detach,
  5185. .transfer = dsi_host_transfer,
  5186. };
  5187. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5188. {
  5189. if (!display || !display->panel) {
  5190. pr_err("invalid param(s)\n");
  5191. return NULL;
  5192. }
  5193. return &display->panel->drm_panel;
  5194. }
  5195. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5196. struct drm_encoder *encoder, struct drm_connector *connector)
  5197. {
  5198. struct drm_device *drm;
  5199. struct drm_bridge *bridge;
  5200. struct drm_bridge *ext_bridge;
  5201. struct drm_connector *ext_conn;
  5202. struct sde_connector *sde_conn;
  5203. struct drm_bridge *prev_bridge;
  5204. int rc = 0, i;
  5205. if (!display || !encoder || !connector)
  5206. return -EINVAL;
  5207. drm = encoder->dev;
  5208. bridge = encoder->bridge;
  5209. sde_conn = to_sde_connector(connector);
  5210. prev_bridge = bridge;
  5211. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5212. return 0;
  5213. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5214. struct dsi_display_ext_bridge *ext_bridge_info =
  5215. &display->ext_bridge[i];
  5216. /* return if ext bridge is already initialized */
  5217. if (ext_bridge_info->bridge)
  5218. return 0;
  5219. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5220. if (IS_ERR_OR_NULL(ext_bridge)) {
  5221. rc = PTR_ERR(ext_bridge);
  5222. DSI_ERR("failed to find ext bridge\n");
  5223. goto error;
  5224. }
  5225. /* override functions for mode adjustment */
  5226. if (display->ext_bridge_cnt > 1) {
  5227. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5228. if (ext_bridge->funcs->mode_fixup)
  5229. ext_bridge_info->bridge_funcs.mode_fixup =
  5230. dsi_display_drm_ext_bridge_mode_fixup;
  5231. if (ext_bridge->funcs->mode_valid)
  5232. ext_bridge_info->bridge_funcs.mode_valid =
  5233. dsi_display_drm_ext_bridge_mode_valid;
  5234. if (ext_bridge->funcs->mode_set)
  5235. ext_bridge_info->bridge_funcs.mode_set =
  5236. dsi_display_drm_ext_bridge_mode_set;
  5237. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5238. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5239. }
  5240. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge);
  5241. if (rc) {
  5242. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5243. display->name, rc);
  5244. goto error;
  5245. }
  5246. ext_bridge_info->display = display;
  5247. ext_bridge_info->bridge = ext_bridge;
  5248. prev_bridge = ext_bridge;
  5249. /* ext bridge will init its own connector during attach,
  5250. * we need to extract it out of the connector list
  5251. */
  5252. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5253. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5254. struct drm_connector, head);
  5255. if (ext_conn && ext_conn != connector &&
  5256. ext_conn->encoder_ids[0] == bridge->encoder->base.id) {
  5257. list_del_init(&ext_conn->head);
  5258. display->ext_conn = ext_conn;
  5259. }
  5260. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5261. /* if there is no valid external connector created, or in split
  5262. * mode, default setting is used from panel defined in DT file.
  5263. */
  5264. if (!display->ext_conn ||
  5265. !display->ext_conn->funcs ||
  5266. !display->ext_conn->helper_private ||
  5267. display->ext_bridge_cnt > 1) {
  5268. display->ext_conn = NULL;
  5269. continue;
  5270. }
  5271. /* otherwise, hook up the functions to use external connector */
  5272. if (display->ext_conn->funcs->detect)
  5273. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5274. if (display->ext_conn->helper_private->get_modes)
  5275. sde_conn->ops.get_modes =
  5276. dsi_display_drm_ext_get_modes;
  5277. if (display->ext_conn->helper_private->mode_valid)
  5278. sde_conn->ops.mode_valid =
  5279. dsi_display_drm_ext_mode_valid;
  5280. if (display->ext_conn->helper_private->atomic_check)
  5281. sde_conn->ops.atomic_check =
  5282. dsi_display_drm_ext_atomic_check;
  5283. sde_conn->ops.get_info =
  5284. dsi_display_ext_get_info;
  5285. sde_conn->ops.get_mode_info =
  5286. dsi_display_ext_get_mode_info;
  5287. /* add support to attach/detach */
  5288. display->host.ops = &dsi_host_ext_ops;
  5289. }
  5290. return 0;
  5291. error:
  5292. return rc;
  5293. }
  5294. int dsi_display_get_info(struct drm_connector *connector,
  5295. struct msm_display_info *info, void *disp)
  5296. {
  5297. struct dsi_display *display;
  5298. struct dsi_panel_phy_props phy_props;
  5299. struct dsi_host_common_cfg *host;
  5300. int i, rc;
  5301. if (!info || !disp) {
  5302. DSI_ERR("invalid params\n");
  5303. return -EINVAL;
  5304. }
  5305. display = disp;
  5306. if (!display->panel) {
  5307. DSI_ERR("invalid display panel\n");
  5308. return -EINVAL;
  5309. }
  5310. mutex_lock(&display->display_lock);
  5311. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5312. if (rc) {
  5313. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5314. display->name, rc);
  5315. goto error;
  5316. }
  5317. memset(info, 0, sizeof(struct msm_display_info));
  5318. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5319. info->num_of_h_tiles = display->ctrl_count;
  5320. for (i = 0; i < info->num_of_h_tiles; i++)
  5321. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5322. info->is_connected = display->is_active;
  5323. if (!strcmp(display->display_type, "primary"))
  5324. info->display_type = SDE_CONNECTOR_PRIMARY;
  5325. else if (!strcmp(display->display_type, "secondary"))
  5326. info->display_type = SDE_CONNECTOR_SECONDARY;
  5327. info->width_mm = phy_props.panel_width_mm;
  5328. info->height_mm = phy_props.panel_height_mm;
  5329. info->max_width = 1920;
  5330. info->max_height = 1080;
  5331. info->qsync_min_fps =
  5332. display->panel->qsync_min_fps;
  5333. info->poms_align_vsync = display->panel->poms_align_vsync;
  5334. switch (display->panel->panel_mode) {
  5335. case DSI_OP_VIDEO_MODE:
  5336. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5337. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5338. if (display->panel->panel_mode_switch_enabled)
  5339. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5340. break;
  5341. case DSI_OP_CMD_MODE:
  5342. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5343. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5344. if (display->panel->panel_mode_switch_enabled)
  5345. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5346. info->is_te_using_watchdog_timer =
  5347. display->panel->te_using_watchdog_timer |
  5348. display->sw_te_using_wd;
  5349. break;
  5350. default:
  5351. DSI_ERR("unknwown dsi panel mode %d\n",
  5352. display->panel->panel_mode);
  5353. break;
  5354. }
  5355. if (display->panel->esd_config.esd_enabled &&
  5356. !display->sw_te_using_wd)
  5357. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5358. info->te_source = display->te_source;
  5359. host = &display->panel->host_config;
  5360. if (host->split_link.split_link_enabled)
  5361. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5362. info->dsc_count = display->panel->dsc_count;
  5363. info->lm_count = display->panel->lm_count;
  5364. error:
  5365. mutex_unlock(&display->display_lock);
  5366. return rc;
  5367. }
  5368. int dsi_display_get_mode_count(struct dsi_display *display,
  5369. u32 *count)
  5370. {
  5371. if (!display || !display->panel) {
  5372. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5373. display ? display->panel != NULL : 0);
  5374. return -EINVAL;
  5375. }
  5376. mutex_lock(&display->display_lock);
  5377. *count = display->panel->num_display_modes;
  5378. mutex_unlock(&display->display_lock);
  5379. return 0;
  5380. }
  5381. void dsi_display_adjust_mode_timing(
  5382. struct dsi_dyn_clk_caps *dyn_clk_caps,
  5383. struct dsi_display_mode *dsi_mode,
  5384. int lanes, int bpp)
  5385. {
  5386. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5387. /* Constant FPS is not supported on command mode */
  5388. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  5389. return;
  5390. if (!dyn_clk_caps->maintain_const_fps)
  5391. return;
  5392. /*
  5393. * When there is a dynamic clock switch, there is small change
  5394. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5395. * is adjusted. It has been assumed that the refined porch values
  5396. * are supported by the panel. This logic can be enhanced further
  5397. * in future by taking min/max porches supported by the panel.
  5398. */
  5399. switch (dyn_clk_caps->type) {
  5400. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5401. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5402. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5403. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5404. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5405. do_div(new_htotal, div);
  5406. if (old_htotal > new_htotal)
  5407. dsi_mode->timing.h_front_porch -=
  5408. (old_htotal - new_htotal);
  5409. else
  5410. dsi_mode->timing.h_front_porch +=
  5411. (new_htotal - old_htotal);
  5412. break;
  5413. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5414. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5415. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5416. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5417. do_div(new_vtotal, div);
  5418. dsi_mode->timing.v_front_porch = new_vtotal -
  5419. dsi_mode->timing.v_back_porch -
  5420. dsi_mode->timing.v_sync_width -
  5421. dsi_mode->timing.v_active;
  5422. break;
  5423. default:
  5424. break;
  5425. }
  5426. }
  5427. static void _dsi_display_populate_bit_clks(struct dsi_display *display,
  5428. int start, int end, u32 *mode_idx)
  5429. {
  5430. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5431. struct dsi_display_mode *src, *dst;
  5432. struct dsi_host_common_cfg *cfg;
  5433. struct dsi_display_mode_priv_info *priv_info;
  5434. int i, j, total_modes, bpp, lanes = 0;
  5435. size_t size = 0;
  5436. if (!display || !mode_idx)
  5437. return;
  5438. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5439. if (!dyn_clk_caps->dyn_clk_support)
  5440. return;
  5441. cfg = &(display->panel->host_config);
  5442. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5443. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5444. lanes++;
  5445. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5446. lanes++;
  5447. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5448. lanes++;
  5449. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5450. lanes++;
  5451. total_modes = display->panel->num_display_modes;
  5452. for (i = start; i < end; i++) {
  5453. src = &display->modes[i];
  5454. if (!src)
  5455. return;
  5456. /*
  5457. * TODO: currently setting the first bit rate in
  5458. * the list as preferred rate. But ideally should
  5459. * be based on user or device tree preferrence.
  5460. */
  5461. src->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[0];
  5462. dsi_display_adjust_mode_timing(dyn_clk_caps, src, lanes, bpp);
  5463. src->pixel_clk_khz =
  5464. div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5465. src->pixel_clk_khz /= 1000;
  5466. src->pixel_clk_khz *= display->ctrl_count;
  5467. }
  5468. for (i = 1; i < dyn_clk_caps->bit_clk_list_len; i++) {
  5469. if (*mode_idx >= total_modes)
  5470. return;
  5471. for (j = start; j < end; j++) {
  5472. src = &display->modes[j];
  5473. dst = &display->modes[*mode_idx];
  5474. if (!src || !dst) {
  5475. DSI_ERR("invalid mode index\n");
  5476. return;
  5477. }
  5478. memcpy(dst, src, sizeof(struct dsi_display_mode));
  5479. size = sizeof(struct dsi_display_mode_priv_info);
  5480. priv_info = kzalloc(size, GFP_KERNEL);
  5481. dst->priv_info = priv_info;
  5482. if (dst->priv_info)
  5483. memcpy(dst->priv_info, src->priv_info, size);
  5484. dst->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[i];
  5485. dsi_display_adjust_mode_timing(dyn_clk_caps, dst, lanes,
  5486. bpp);
  5487. dst->pixel_clk_khz =
  5488. div_u64(dst->timing.clk_rate_hz * lanes, bpp);
  5489. dst->pixel_clk_khz /= 1000;
  5490. dst->pixel_clk_khz *= display->ctrl_count;
  5491. (*mode_idx)++;
  5492. }
  5493. }
  5494. }
  5495. void dsi_display_put_mode(struct dsi_display *display,
  5496. struct dsi_display_mode *mode)
  5497. {
  5498. dsi_panel_put_mode(mode);
  5499. }
  5500. int dsi_display_get_modes(struct dsi_display *display,
  5501. struct dsi_display_mode **out_modes)
  5502. {
  5503. struct dsi_dfps_capabilities dfps_caps;
  5504. struct dsi_display_ctrl *ctrl;
  5505. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5506. bool is_split_link, is_cmd_mode;
  5507. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5508. u32 sublinks_count, mode_idx, array_idx = 0;
  5509. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5510. int i, start, end, rc = -EINVAL;
  5511. if (!display || !out_modes) {
  5512. DSI_ERR("Invalid params\n");
  5513. return -EINVAL;
  5514. }
  5515. *out_modes = NULL;
  5516. ctrl = &display->ctrl[0];
  5517. mutex_lock(&display->display_lock);
  5518. if (display->modes)
  5519. goto exit;
  5520. display_mode_count = display->panel->num_display_modes;
  5521. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5522. GFP_KERNEL);
  5523. if (!display->modes) {
  5524. rc = -ENOMEM;
  5525. goto error;
  5526. }
  5527. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5528. if (rc) {
  5529. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5530. display->name);
  5531. goto error;
  5532. }
  5533. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5534. timing_mode_count = display->panel->num_timing_nodes;
  5535. /* Validate command line timing */
  5536. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5537. (display->cmdline_timing >= timing_mode_count))
  5538. display->cmdline_timing = NO_OVERRIDE;
  5539. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5540. struct dsi_display_mode display_mode;
  5541. int topology_override = NO_OVERRIDE;
  5542. bool is_preferred = false;
  5543. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5544. if (display->cmdline_timing == mode_idx) {
  5545. topology_override = display->cmdline_topology;
  5546. is_preferred = true;
  5547. }
  5548. memset(&display_mode, 0, sizeof(display_mode));
  5549. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5550. &display_mode,
  5551. topology_override);
  5552. if (rc) {
  5553. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5554. display->name, mode_idx);
  5555. goto error;
  5556. }
  5557. is_cmd_mode = (display_mode.panel_mode == DSI_OP_CMD_MODE);
  5558. /* Setup widebus support */
  5559. display_mode.priv_info->widebus_support =
  5560. ctrl->ctrl->hw.widebus_support;
  5561. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5562. is_cmd_mode) ? 1 : dfps_caps.dfps_list_len);
  5563. /* Calculate dsi frame transfer time */
  5564. if (is_cmd_mode) {
  5565. dsi_panel_calc_dsi_transfer_time(
  5566. &display->panel->host_config,
  5567. &display_mode, frame_threshold_us);
  5568. display_mode.priv_info->dsi_transfer_time_us =
  5569. display_mode.timing.dsi_transfer_time_us;
  5570. display_mode.priv_info->min_dsi_clk_hz =
  5571. display_mode.timing.min_dsi_clk_hz;
  5572. display_mode.priv_info->mdp_transfer_time_us =
  5573. display_mode.timing.mdp_transfer_time_us;
  5574. }
  5575. is_split_link = host->split_link.split_link_enabled;
  5576. sublinks_count = host->split_link.num_sublinks;
  5577. if (is_split_link && sublinks_count > 1) {
  5578. display_mode.timing.h_active *= sublinks_count;
  5579. display_mode.timing.h_front_porch *= sublinks_count;
  5580. display_mode.timing.h_sync_width *= sublinks_count;
  5581. display_mode.timing.h_back_porch *= sublinks_count;
  5582. display_mode.timing.h_skew *= sublinks_count;
  5583. display_mode.pixel_clk_khz *= sublinks_count;
  5584. } else {
  5585. display_mode.timing.h_active *= display->ctrl_count;
  5586. display_mode.timing.h_front_porch *=
  5587. display->ctrl_count;
  5588. display_mode.timing.h_sync_width *=
  5589. display->ctrl_count;
  5590. display_mode.timing.h_back_porch *=
  5591. display->ctrl_count;
  5592. display_mode.timing.h_skew *= display->ctrl_count;
  5593. display_mode.pixel_clk_khz *= display->ctrl_count;
  5594. }
  5595. start = array_idx;
  5596. for (i = 0; i < num_dfps_rates; i++) {
  5597. struct dsi_display_mode *sub_mode =
  5598. &display->modes[array_idx];
  5599. u32 curr_refresh_rate;
  5600. if (!sub_mode) {
  5601. DSI_ERR("invalid mode data\n");
  5602. rc = -EFAULT;
  5603. goto error;
  5604. }
  5605. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5606. array_idx++;
  5607. if (!dfps_caps.dfps_support || is_cmd_mode)
  5608. continue;
  5609. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5610. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5611. dsi_display_get_dfps_timing(display, sub_mode,
  5612. curr_refresh_rate);
  5613. }
  5614. end = array_idx;
  5615. /*
  5616. * if POMS is enabled and boot up mode is video mode,
  5617. * skip bit clk rates update for command mode,
  5618. * else if dynamic clk switch is supported then update all
  5619. * the bit clk rates.
  5620. */
  5621. if (is_cmd_mode &&
  5622. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  5623. continue;
  5624. _dsi_display_populate_bit_clks(display, start, end, &array_idx);
  5625. if (is_preferred) {
  5626. /* Set first timing sub mode as preferred mode */
  5627. display->modes[start].is_preferred = true;
  5628. }
  5629. }
  5630. exit:
  5631. *out_modes = display->modes;
  5632. rc = 0;
  5633. error:
  5634. if (rc)
  5635. kfree(display->modes);
  5636. mutex_unlock(&display->display_lock);
  5637. return rc;
  5638. }
  5639. int dsi_display_get_panel_vfp(void *dsi_display,
  5640. int h_active, int v_active)
  5641. {
  5642. int i, rc = 0;
  5643. u32 count, refresh_rate = 0;
  5644. struct dsi_dfps_capabilities dfps_caps;
  5645. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5646. struct dsi_host_common_cfg *host;
  5647. if (!display || !display->panel)
  5648. return -EINVAL;
  5649. mutex_lock(&display->display_lock);
  5650. count = display->panel->num_display_modes;
  5651. if (display->panel->cur_mode)
  5652. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5653. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5654. if (dfps_caps.dfps_support)
  5655. refresh_rate = dfps_caps.max_refresh_rate;
  5656. if (!refresh_rate) {
  5657. mutex_unlock(&display->display_lock);
  5658. DSI_ERR("Null Refresh Rate\n");
  5659. return -EINVAL;
  5660. }
  5661. host = &display->panel->host_config;
  5662. if (host->split_link.split_link_enabled)
  5663. h_active *= host->split_link.num_sublinks;
  5664. else
  5665. h_active *= display->ctrl_count;
  5666. for (i = 0; i < count; i++) {
  5667. struct dsi_display_mode *m = &display->modes[i];
  5668. if (m && v_active == m->timing.v_active &&
  5669. h_active == m->timing.h_active &&
  5670. refresh_rate == m->timing.refresh_rate) {
  5671. rc = m->timing.v_front_porch;
  5672. break;
  5673. }
  5674. }
  5675. mutex_unlock(&display->display_lock);
  5676. return rc;
  5677. }
  5678. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5679. {
  5680. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5681. u32 count, i;
  5682. int rc = 0;
  5683. *num_lm = 0;
  5684. mutex_lock(&display->display_lock);
  5685. count = display->panel->num_display_modes;
  5686. mutex_unlock(&display->display_lock);
  5687. if (!display->modes) {
  5688. struct dsi_display_mode *m;
  5689. rc = dsi_display_get_modes(display, &m);
  5690. if (rc)
  5691. return rc;
  5692. }
  5693. mutex_lock(&display->display_lock);
  5694. for (i = 0; i < count; i++) {
  5695. struct dsi_display_mode *m = &display->modes[i];
  5696. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5697. }
  5698. mutex_unlock(&display->display_lock);
  5699. return rc;
  5700. }
  5701. int dsi_display_find_mode(struct dsi_display *display,
  5702. const struct dsi_display_mode *cmp,
  5703. struct dsi_display_mode **out_mode)
  5704. {
  5705. u32 count, i;
  5706. int rc;
  5707. if (!display || !out_mode)
  5708. return -EINVAL;
  5709. *out_mode = NULL;
  5710. mutex_lock(&display->display_lock);
  5711. count = display->panel->num_display_modes;
  5712. mutex_unlock(&display->display_lock);
  5713. if (!display->modes) {
  5714. struct dsi_display_mode *m;
  5715. rc = dsi_display_get_modes(display, &m);
  5716. if (rc)
  5717. return rc;
  5718. }
  5719. mutex_lock(&display->display_lock);
  5720. for (i = 0; i < count; i++) {
  5721. struct dsi_display_mode *m = &display->modes[i];
  5722. if (cmp->timing.v_active == m->timing.v_active &&
  5723. cmp->timing.h_active == m->timing.h_active &&
  5724. cmp->timing.refresh_rate == m->timing.refresh_rate &&
  5725. cmp->panel_mode == m->panel_mode &&
  5726. cmp->pixel_clk_khz == m->pixel_clk_khz) {
  5727. *out_mode = m;
  5728. rc = 0;
  5729. break;
  5730. }
  5731. }
  5732. mutex_unlock(&display->display_lock);
  5733. if (!*out_mode) {
  5734. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  5735. display->name, cmp->timing.v_active,
  5736. cmp->timing.h_active, cmp->timing.refresh_rate,
  5737. cmp->pixel_clk_khz);
  5738. rc = -ENOENT;
  5739. }
  5740. return rc;
  5741. }
  5742. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  5743. struct dsi_display_mode *adj)
  5744. {
  5745. /*
  5746. * If there is a change in the hfp or vfp of the current and adjoining
  5747. * mode,then either it is a dfps mode switch or dynamic clk change with
  5748. * constant fps.
  5749. */
  5750. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  5751. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  5752. return true;
  5753. else
  5754. return false;
  5755. }
  5756. /**
  5757. * dsi_display_validate_mode_change() - Validate mode change case.
  5758. * @display: DSI display handle.
  5759. * @cur_mode: Current mode.
  5760. * @adj_mode: Mode to be set.
  5761. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  5762. * is change in hfp or vfp but vactive and hactive are same.
  5763. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  5764. * is change in clk but vactive and hactive are same.
  5765. * Return: error code.
  5766. */
  5767. int dsi_display_validate_mode_change(struct dsi_display *display,
  5768. struct dsi_display_mode *cur_mode,
  5769. struct dsi_display_mode *adj_mode)
  5770. {
  5771. int rc = 0;
  5772. struct dsi_dfps_capabilities dfps_caps;
  5773. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5774. if (!display || !adj_mode) {
  5775. DSI_ERR("Invalid params\n");
  5776. return -EINVAL;
  5777. }
  5778. if (!display->panel || !display->panel->cur_mode) {
  5779. DSI_DEBUG("Current panel mode not set\n");
  5780. return rc;
  5781. }
  5782. mutex_lock(&display->display_lock);
  5783. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5784. if ((cur_mode->timing.v_active == adj_mode->timing.v_active) &&
  5785. (cur_mode->timing.h_active == adj_mode->timing.h_active) &&
  5786. (cur_mode->panel_mode == adj_mode->panel_mode)) {
  5787. /* dfps and dynamic clock with const fps use case */
  5788. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  5789. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5790. if (dfps_caps.dfps_support ||
  5791. dyn_clk_caps->maintain_const_fps) {
  5792. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  5793. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  5794. SDE_EVT32(cur_mode->timing.refresh_rate,
  5795. adj_mode->timing.refresh_rate,
  5796. cur_mode->timing.h_front_porch,
  5797. adj_mode->timing.h_front_porch);
  5798. }
  5799. }
  5800. /* dynamic clk change use case */
  5801. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  5802. if (dyn_clk_caps->dyn_clk_support) {
  5803. DSI_DEBUG("dynamic clk change detected\n");
  5804. if ((adj_mode->dsi_mode_flags &
  5805. DSI_MODE_FLAG_VRR) &&
  5806. (!dyn_clk_caps->maintain_const_fps)) {
  5807. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  5808. rc = -ENOTSUPP;
  5809. goto error;
  5810. }
  5811. adj_mode->dsi_mode_flags |=
  5812. DSI_MODE_FLAG_DYN_CLK;
  5813. SDE_EVT32(cur_mode->pixel_clk_khz,
  5814. adj_mode->pixel_clk_khz);
  5815. }
  5816. }
  5817. }
  5818. error:
  5819. mutex_unlock(&display->display_lock);
  5820. return rc;
  5821. }
  5822. int dsi_display_validate_mode(struct dsi_display *display,
  5823. struct dsi_display_mode *mode,
  5824. u32 flags)
  5825. {
  5826. int rc = 0;
  5827. int i;
  5828. struct dsi_display_ctrl *ctrl;
  5829. struct dsi_display_mode adj_mode;
  5830. if (!display || !mode) {
  5831. DSI_ERR("Invalid params\n");
  5832. return -EINVAL;
  5833. }
  5834. mutex_lock(&display->display_lock);
  5835. adj_mode = *mode;
  5836. adjust_timing_by_ctrl_count(display, &adj_mode);
  5837. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  5838. if (rc) {
  5839. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  5840. display->name, rc);
  5841. goto error;
  5842. }
  5843. display_for_each_ctrl(i, display) {
  5844. ctrl = &display->ctrl[i];
  5845. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  5846. if (rc) {
  5847. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  5848. display->name, rc);
  5849. goto error;
  5850. }
  5851. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  5852. if (rc) {
  5853. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  5854. display->name, rc);
  5855. goto error;
  5856. }
  5857. }
  5858. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  5859. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  5860. rc = dsi_display_validate_mode_seamless(display, mode);
  5861. if (rc) {
  5862. DSI_ERR("[%s] seamless not possible rc=%d\n",
  5863. display->name, rc);
  5864. goto error;
  5865. }
  5866. }
  5867. error:
  5868. mutex_unlock(&display->display_lock);
  5869. return rc;
  5870. }
  5871. int dsi_display_set_mode(struct dsi_display *display,
  5872. struct dsi_display_mode *mode,
  5873. u32 flags)
  5874. {
  5875. int rc = 0;
  5876. struct dsi_display_mode adj_mode;
  5877. struct dsi_mode_info timing;
  5878. if (!display || !mode || !display->panel) {
  5879. DSI_ERR("Invalid params\n");
  5880. return -EINVAL;
  5881. }
  5882. mutex_lock(&display->display_lock);
  5883. adj_mode = *mode;
  5884. timing = adj_mode.timing;
  5885. adjust_timing_by_ctrl_count(display, &adj_mode);
  5886. if (!display->panel->cur_mode) {
  5887. display->panel->cur_mode =
  5888. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  5889. if (!display->panel->cur_mode) {
  5890. rc = -ENOMEM;
  5891. goto error;
  5892. }
  5893. }
  5894. /*For dynamic DSI setting, use specified clock rate */
  5895. if (display->cached_clk_rate > 0)
  5896. adj_mode.priv_info->clk_rate_hz = display->cached_clk_rate;
  5897. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  5898. if (rc) {
  5899. DSI_ERR("[%s] mode cannot be set\n", display->name);
  5900. goto error;
  5901. }
  5902. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  5903. if (rc) {
  5904. DSI_ERR("[%s] failed to set mode\n", display->name);
  5905. goto error;
  5906. }
  5907. DSI_INFO("mdp_transfer_time_us=%d us\n",
  5908. adj_mode.priv_info->mdp_transfer_time_us);
  5909. DSI_INFO("hactive= %d,vactive= %d,fps=%d\n",
  5910. timing.h_active, timing.v_active,
  5911. timing.refresh_rate);
  5912. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  5913. error:
  5914. mutex_unlock(&display->display_lock);
  5915. return rc;
  5916. }
  5917. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  5918. {
  5919. int rc = 0;
  5920. int i;
  5921. struct dsi_display_ctrl *ctrl;
  5922. if (!display) {
  5923. DSI_ERR("Invalid params\n");
  5924. return -EINVAL;
  5925. }
  5926. display_for_each_ctrl(i, display) {
  5927. ctrl = &display->ctrl[i];
  5928. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  5929. if (rc) {
  5930. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  5931. display->name, i);
  5932. goto error;
  5933. }
  5934. }
  5935. display->is_tpg_enabled = enable;
  5936. error:
  5937. return rc;
  5938. }
  5939. static int dsi_display_pre_switch(struct dsi_display *display)
  5940. {
  5941. int rc = 0;
  5942. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  5943. DSI_CORE_CLK, DSI_CLK_ON);
  5944. if (rc) {
  5945. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  5946. display->name, rc);
  5947. goto error;
  5948. }
  5949. rc = dsi_display_ctrl_update(display);
  5950. if (rc) {
  5951. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  5952. display->name, rc);
  5953. goto error_ctrl_clk_off;
  5954. }
  5955. if (!display->trusted_vm_env) {
  5956. rc = dsi_display_set_clk_src(display);
  5957. if (rc) {
  5958. DSI_ERR(
  5959. "[%s] failed to set DSI link clock source, rc=%d\n",
  5960. display->name, rc);
  5961. goto error_ctrl_deinit;
  5962. }
  5963. }
  5964. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  5965. DSI_LINK_CLK, DSI_CLK_ON);
  5966. if (rc) {
  5967. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  5968. display->name, rc);
  5969. goto error_ctrl_deinit;
  5970. }
  5971. goto error;
  5972. error_ctrl_deinit:
  5973. (void)dsi_display_ctrl_deinit(display);
  5974. error_ctrl_clk_off:
  5975. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  5976. DSI_CORE_CLK, DSI_CLK_OFF);
  5977. error:
  5978. return rc;
  5979. }
  5980. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  5981. {
  5982. int i;
  5983. struct dsi_display_ctrl *ctrl;
  5984. display_for_each_ctrl(i, display) {
  5985. ctrl = &display->ctrl[i];
  5986. if (!ctrl->ctrl)
  5987. continue;
  5988. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  5989. return false;
  5990. }
  5991. return true;
  5992. }
  5993. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  5994. {
  5995. struct dsi_display *display = NULL;
  5996. display = container_of(work, struct dsi_display, fifo_underflow_work);
  5997. if (!display || !display->panel ||
  5998. atomic_read(&display->panel->esd_recovery_pending)) {
  5999. DSI_DEBUG("Invalid recovery use case\n");
  6000. return;
  6001. }
  6002. mutex_lock(&display->display_lock);
  6003. if (!_dsi_display_validate_host_state(display)) {
  6004. mutex_unlock(&display->display_lock);
  6005. return;
  6006. }
  6007. DSI_INFO("handle DSI FIFO underflow error\n");
  6008. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6009. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6010. DSI_ALL_CLKS, DSI_CLK_ON);
  6011. dsi_display_soft_reset(display);
  6012. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6013. DSI_ALL_CLKS, DSI_CLK_OFF);
  6014. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6015. mutex_unlock(&display->display_lock);
  6016. }
  6017. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6018. {
  6019. struct dsi_display *display = NULL;
  6020. struct dsi_display_ctrl *ctrl;
  6021. int i, rc;
  6022. int mask = BIT(20); /* clock lane */
  6023. int (*cb_func)(void *event_usr_ptr,
  6024. uint32_t event_idx, uint32_t instance_idx,
  6025. uint32_t data0, uint32_t data1,
  6026. uint32_t data2, uint32_t data3);
  6027. void *data;
  6028. u32 version = 0;
  6029. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6030. if (!display || !display->panel ||
  6031. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6032. atomic_read(&display->panel->esd_recovery_pending)) {
  6033. DSI_DEBUG("Invalid recovery use case\n");
  6034. return;
  6035. }
  6036. mutex_lock(&display->display_lock);
  6037. if (!_dsi_display_validate_host_state(display)) {
  6038. mutex_unlock(&display->display_lock);
  6039. return;
  6040. }
  6041. DSI_INFO("handle DSI FIFO overflow error\n");
  6042. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6043. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6044. DSI_ALL_CLKS, DSI_CLK_ON);
  6045. /*
  6046. * below recovery sequence is not applicable to
  6047. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6048. */
  6049. ctrl = &display->ctrl[display->clk_master_idx];
  6050. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6051. if (!version || (version < 0x20020001))
  6052. goto end;
  6053. /* reset ctrl and lanes */
  6054. display_for_each_ctrl(i, display) {
  6055. ctrl = &display->ctrl[i];
  6056. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6057. rc = dsi_phy_lane_reset(ctrl->phy);
  6058. }
  6059. /* wait for display line count to be in active area */
  6060. ctrl = &display->ctrl[display->clk_master_idx];
  6061. if (ctrl->ctrl->recovery_cb.event_cb) {
  6062. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6063. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6064. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6065. display->clk_master_idx, 0, 0, 0, 0);
  6066. if (rc < 0) {
  6067. DSI_DEBUG("sde callback failed\n");
  6068. goto end;
  6069. }
  6070. }
  6071. /* Enable Video mode for DSI controller */
  6072. display_for_each_ctrl(i, display) {
  6073. ctrl = &display->ctrl[i];
  6074. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6075. }
  6076. /*
  6077. * Add sufficient delay to make sure
  6078. * pixel transmission has started
  6079. */
  6080. udelay(200);
  6081. end:
  6082. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6083. DSI_ALL_CLKS, DSI_CLK_OFF);
  6084. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6085. mutex_unlock(&display->display_lock);
  6086. }
  6087. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6088. {
  6089. struct dsi_display *display = NULL;
  6090. struct dsi_display_ctrl *ctrl;
  6091. int i, rc;
  6092. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6093. int (*cb_func)(void *event_usr_ptr,
  6094. uint32_t event_idx, uint32_t instance_idx,
  6095. uint32_t data0, uint32_t data1,
  6096. uint32_t data2, uint32_t data3);
  6097. void *data;
  6098. u32 version = 0;
  6099. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6100. if (!display || !display->panel ||
  6101. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6102. atomic_read(&display->panel->esd_recovery_pending)) {
  6103. DSI_DEBUG("Invalid recovery use case\n");
  6104. return;
  6105. }
  6106. mutex_lock(&display->display_lock);
  6107. if (!_dsi_display_validate_host_state(display)) {
  6108. mutex_unlock(&display->display_lock);
  6109. return;
  6110. }
  6111. DSI_INFO("handle DSI LP RX Timeout error\n");
  6112. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6113. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6114. DSI_ALL_CLKS, DSI_CLK_ON);
  6115. /*
  6116. * below recovery sequence is not applicable to
  6117. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6118. */
  6119. ctrl = &display->ctrl[display->clk_master_idx];
  6120. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6121. if (!version || (version < 0x20020001))
  6122. goto end;
  6123. /* reset ctrl and lanes */
  6124. display_for_each_ctrl(i, display) {
  6125. ctrl = &display->ctrl[i];
  6126. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6127. rc = dsi_phy_lane_reset(ctrl->phy);
  6128. }
  6129. ctrl = &display->ctrl[display->clk_master_idx];
  6130. if (ctrl->ctrl->recovery_cb.event_cb) {
  6131. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6132. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6133. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6134. display->clk_master_idx, 0, 0, 0, 0);
  6135. if (rc < 0) {
  6136. DSI_DEBUG("Target is in suspend/shutdown\n");
  6137. goto end;
  6138. }
  6139. }
  6140. /* Enable Video mode for DSI controller */
  6141. display_for_each_ctrl(i, display) {
  6142. ctrl = &display->ctrl[i];
  6143. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6144. }
  6145. /*
  6146. * Add sufficient delay to make sure
  6147. * pixel transmission as started
  6148. */
  6149. udelay(200);
  6150. end:
  6151. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6152. DSI_ALL_CLKS, DSI_CLK_OFF);
  6153. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6154. mutex_unlock(&display->display_lock);
  6155. }
  6156. static int dsi_display_cb_error_handler(void *data,
  6157. uint32_t event_idx, uint32_t instance_idx,
  6158. uint32_t data0, uint32_t data1,
  6159. uint32_t data2, uint32_t data3)
  6160. {
  6161. struct dsi_display *display = data;
  6162. if (!display || !(display->err_workq))
  6163. return -EINVAL;
  6164. switch (event_idx) {
  6165. case DSI_FIFO_UNDERFLOW:
  6166. queue_work(display->err_workq, &display->fifo_underflow_work);
  6167. break;
  6168. case DSI_FIFO_OVERFLOW:
  6169. queue_work(display->err_workq, &display->fifo_overflow_work);
  6170. break;
  6171. case DSI_LP_Rx_TIMEOUT:
  6172. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6173. break;
  6174. default:
  6175. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6176. break;
  6177. }
  6178. return 0;
  6179. }
  6180. static void dsi_display_register_error_handler(struct dsi_display *display)
  6181. {
  6182. int i = 0;
  6183. struct dsi_display_ctrl *ctrl;
  6184. struct dsi_event_cb_info event_info;
  6185. if (!display)
  6186. return;
  6187. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6188. if (!display->err_workq) {
  6189. DSI_ERR("failed to create dsi workq!\n");
  6190. return;
  6191. }
  6192. INIT_WORK(&display->fifo_underflow_work,
  6193. dsi_display_handle_fifo_underflow);
  6194. INIT_WORK(&display->fifo_overflow_work,
  6195. dsi_display_handle_fifo_overflow);
  6196. INIT_WORK(&display->lp_rx_timeout_work,
  6197. dsi_display_handle_lp_rx_timeout);
  6198. memset(&event_info, 0, sizeof(event_info));
  6199. event_info.event_cb = dsi_display_cb_error_handler;
  6200. event_info.event_usr_ptr = display;
  6201. display_for_each_ctrl(i, display) {
  6202. ctrl = &display->ctrl[i];
  6203. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6204. }
  6205. }
  6206. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6207. {
  6208. int i = 0;
  6209. struct dsi_display_ctrl *ctrl;
  6210. if (!display)
  6211. return;
  6212. display_for_each_ctrl(i, display) {
  6213. ctrl = &display->ctrl[i];
  6214. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6215. 0, sizeof(struct dsi_event_cb_info));
  6216. }
  6217. if (display->err_workq) {
  6218. destroy_workqueue(display->err_workq);
  6219. display->err_workq = NULL;
  6220. }
  6221. }
  6222. int dsi_display_prepare(struct dsi_display *display)
  6223. {
  6224. int rc = 0;
  6225. struct dsi_display_mode *mode;
  6226. if (!display) {
  6227. DSI_ERR("Invalid params\n");
  6228. return -EINVAL;
  6229. }
  6230. if (!display->panel->cur_mode) {
  6231. DSI_ERR("no valid mode set for the display\n");
  6232. return -EINVAL;
  6233. }
  6234. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6235. mutex_lock(&display->display_lock);
  6236. mode = display->panel->cur_mode;
  6237. dsi_display_set_ctrl_esd_check_flag(display, false);
  6238. /* Set up ctrl isr before enabling core clk */
  6239. if (!display->trusted_vm_env)
  6240. dsi_display_ctrl_isr_configure(display, true);
  6241. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6242. if (display->is_cont_splash_enabled &&
  6243. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6244. DSI_ERR("DMS not supported on first frame\n");
  6245. rc = -EINVAL;
  6246. goto error;
  6247. }
  6248. if (!is_skip_op_required(display)) {
  6249. /* update dsi ctrl for new mode */
  6250. rc = dsi_display_pre_switch(display);
  6251. if (rc)
  6252. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6253. display->name, rc);
  6254. goto error;
  6255. }
  6256. }
  6257. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) &&
  6258. (!is_skip_op_required(display))) {
  6259. /*
  6260. * For continuous splash/trusted vm, we skip panel
  6261. * pre prepare since the regulator vote is already
  6262. * taken care in splash resource init
  6263. */
  6264. rc = dsi_panel_pre_prepare(display->panel);
  6265. if (rc) {
  6266. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6267. display->name, rc);
  6268. goto error;
  6269. }
  6270. }
  6271. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6272. DSI_CORE_CLK, DSI_CLK_ON);
  6273. if (rc) {
  6274. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6275. display->name, rc);
  6276. goto error_panel_post_unprep;
  6277. }
  6278. /*
  6279. * If ULPS during suspend feature is enabled, then DSI PHY was
  6280. * left on during suspend. In this case, we do not need to reset/init
  6281. * PHY. This would have already been done when the CORE clocks are
  6282. * turned on. However, if cont splash is disabled, the first time DSI
  6283. * is powered on, phy init needs to be done unconditionally.
  6284. */
  6285. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6286. rc = dsi_display_phy_sw_reset(display);
  6287. if (rc) {
  6288. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6289. display->name, rc);
  6290. goto error_ctrl_clk_off;
  6291. }
  6292. rc = dsi_display_phy_enable(display);
  6293. if (rc) {
  6294. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6295. display->name, rc);
  6296. goto error_ctrl_clk_off;
  6297. }
  6298. }
  6299. if (!display->trusted_vm_env) {
  6300. rc = dsi_display_set_clk_src(display);
  6301. if (rc) {
  6302. DSI_ERR(
  6303. "[%s] failed to set DSI link clock source, rc=%d\n",
  6304. display->name, rc);
  6305. goto error_phy_disable;
  6306. }
  6307. }
  6308. rc = dsi_display_ctrl_init(display);
  6309. if (rc) {
  6310. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6311. display->name, rc);
  6312. goto error_phy_disable;
  6313. }
  6314. /* Set up DSI ERROR event callback */
  6315. dsi_display_register_error_handler(display);
  6316. rc = dsi_display_ctrl_host_enable(display);
  6317. if (rc) {
  6318. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6319. display->name, rc);
  6320. goto error_ctrl_deinit;
  6321. }
  6322. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6323. DSI_LINK_CLK, DSI_CLK_ON);
  6324. if (rc) {
  6325. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6326. display->name, rc);
  6327. goto error_host_engine_off;
  6328. }
  6329. if (!is_skip_op_required(display)) {
  6330. /*
  6331. * For continuous splash/trusted vm, skip panel prepare and
  6332. * ctl reset since the pnael and ctrl is already in active
  6333. * state and panel on commands are not needed
  6334. */
  6335. rc = dsi_display_soft_reset(display);
  6336. if (rc) {
  6337. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6338. display->name, rc);
  6339. goto error_ctrl_link_off;
  6340. }
  6341. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)) {
  6342. rc = dsi_panel_prepare(display->panel);
  6343. if (rc) {
  6344. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6345. display->name, rc);
  6346. goto error_ctrl_link_off;
  6347. }
  6348. }
  6349. }
  6350. goto error;
  6351. error_ctrl_link_off:
  6352. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6353. DSI_LINK_CLK, DSI_CLK_OFF);
  6354. error_host_engine_off:
  6355. (void)dsi_display_ctrl_host_disable(display);
  6356. error_ctrl_deinit:
  6357. (void)dsi_display_ctrl_deinit(display);
  6358. error_phy_disable:
  6359. (void)dsi_display_phy_disable(display);
  6360. error_ctrl_clk_off:
  6361. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6362. DSI_CORE_CLK, DSI_CLK_OFF);
  6363. error_panel_post_unprep:
  6364. (void)dsi_panel_post_unprepare(display->panel);
  6365. error:
  6366. mutex_unlock(&display->display_lock);
  6367. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6368. return rc;
  6369. }
  6370. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6371. const struct dsi_display_ctrl *ctrl,
  6372. const struct msm_roi_list *req_rois,
  6373. struct dsi_rect *out_roi)
  6374. {
  6375. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6376. struct dsi_display_mode *cur_mode;
  6377. struct msm_roi_caps *roi_caps;
  6378. struct dsi_rect req_roi = { 0 };
  6379. int rc = 0;
  6380. cur_mode = display->panel->cur_mode;
  6381. if (!cur_mode)
  6382. return 0;
  6383. roi_caps = &cur_mode->priv_info->roi_caps;
  6384. if (req_rois->num_rects > roi_caps->num_roi) {
  6385. DSI_ERR("request for %d rois greater than max %d\n",
  6386. req_rois->num_rects,
  6387. roi_caps->num_roi);
  6388. rc = -EINVAL;
  6389. goto exit;
  6390. }
  6391. /**
  6392. * if no rois, user wants to reset back to full resolution
  6393. * note: h_active is already divided by ctrl_count
  6394. */
  6395. if (!req_rois->num_rects) {
  6396. *out_roi = *bounds;
  6397. goto exit;
  6398. }
  6399. /* intersect with the bounds */
  6400. req_roi.x = req_rois->roi[0].x1;
  6401. req_roi.y = req_rois->roi[0].y1;
  6402. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6403. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6404. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6405. exit:
  6406. /* adjust the ctrl origin to be top left within the ctrl */
  6407. out_roi->x = out_roi->x - bounds->x;
  6408. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6409. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6410. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6411. bounds->x, bounds->y, bounds->w, bounds->h,
  6412. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6413. return rc;
  6414. }
  6415. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6416. {
  6417. int i;
  6418. int rc = 0;
  6419. if (!display->panel->qsync_min_fps) {
  6420. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6421. return 0;
  6422. }
  6423. mutex_lock(&display->display_lock);
  6424. display_for_each_ctrl(i, display) {
  6425. if (enable) {
  6426. /* send the commands to enable qsync */
  6427. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6428. if (rc) {
  6429. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6430. goto exit;
  6431. }
  6432. } else {
  6433. /* send the commands to enable qsync */
  6434. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6435. if (rc) {
  6436. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6437. goto exit;
  6438. }
  6439. }
  6440. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6441. }
  6442. exit:
  6443. SDE_EVT32(enable, display->panel->qsync_min_fps, rc);
  6444. mutex_unlock(&display->display_lock);
  6445. return rc;
  6446. }
  6447. static int dsi_display_set_roi(struct dsi_display *display,
  6448. struct msm_roi_list *rois)
  6449. {
  6450. struct dsi_display_mode *cur_mode;
  6451. struct msm_roi_caps *roi_caps;
  6452. int rc = 0;
  6453. int i;
  6454. if (!display || !rois || !display->panel)
  6455. return -EINVAL;
  6456. cur_mode = display->panel->cur_mode;
  6457. if (!cur_mode)
  6458. return 0;
  6459. roi_caps = &cur_mode->priv_info->roi_caps;
  6460. if (!roi_caps->enabled)
  6461. return 0;
  6462. display_for_each_ctrl(i, display) {
  6463. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6464. struct dsi_rect ctrl_roi;
  6465. bool changed = false;
  6466. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6467. if (rc) {
  6468. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6469. return rc;
  6470. }
  6471. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6472. if (rc) {
  6473. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6474. return rc;
  6475. }
  6476. if (!changed)
  6477. continue;
  6478. /* send the new roi to the panel via dcs commands */
  6479. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6480. if (rc) {
  6481. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6482. return rc;
  6483. }
  6484. /* re-program the ctrl with the timing based on the new roi */
  6485. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6486. if (rc) {
  6487. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6488. return rc;
  6489. }
  6490. }
  6491. return rc;
  6492. }
  6493. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6494. struct dsi_display *display,
  6495. struct msm_display_kickoff_params *params)
  6496. {
  6497. int rc = 0, ret = 0;
  6498. int i;
  6499. /* check and setup MISR */
  6500. if (display->misr_enable)
  6501. _dsi_display_setup_misr(display);
  6502. /* dynamic DSI clock setting */
  6503. if (atomic_read(&display->clkrate_change_pending)) {
  6504. mutex_lock(&display->display_lock);
  6505. /*
  6506. * acquire panel_lock to make sure no commands are in progress
  6507. */
  6508. dsi_panel_acquire_panel_lock(display->panel);
  6509. /*
  6510. * Wait for DSI command engine not to be busy sending data
  6511. * from display engine.
  6512. * If waiting fails, return "rc" instead of below "ret" so as
  6513. * not to impact DRM commit. The clock updating would be
  6514. * deferred to the next DRM commit.
  6515. */
  6516. display_for_each_ctrl(i, display) {
  6517. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6518. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6519. if (ret)
  6520. goto wait_failure;
  6521. }
  6522. /*
  6523. * Don't check the return value so as not to impact DRM commit
  6524. * when error occurs.
  6525. */
  6526. (void)dsi_display_force_update_dsi_clk(display);
  6527. wait_failure:
  6528. /* release panel_lock */
  6529. dsi_panel_release_panel_lock(display->panel);
  6530. mutex_unlock(&display->display_lock);
  6531. }
  6532. if (!ret)
  6533. rc = dsi_display_set_roi(display, params->rois);
  6534. return rc;
  6535. }
  6536. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6537. {
  6538. int rc = 0;
  6539. if (!display || !display->panel) {
  6540. DSI_ERR("Invalid params\n");
  6541. return -EINVAL;
  6542. }
  6543. if (!display->panel->cur_mode) {
  6544. DSI_ERR("no valid mode set for the display\n");
  6545. return -EINVAL;
  6546. }
  6547. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6548. rc = dsi_display_vid_engine_enable(display);
  6549. if (rc) {
  6550. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6551. display->name, rc);
  6552. goto error_out;
  6553. }
  6554. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6555. rc = dsi_display_cmd_engine_enable(display);
  6556. if (rc) {
  6557. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6558. display->name, rc);
  6559. goto error_out;
  6560. }
  6561. } else {
  6562. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6563. rc = -EINVAL;
  6564. }
  6565. error_out:
  6566. return rc;
  6567. }
  6568. int dsi_display_pre_commit(void *display,
  6569. struct msm_display_conn_params *params)
  6570. {
  6571. bool enable = false;
  6572. int rc = 0;
  6573. if (!display || !params) {
  6574. pr_err("Invalid params\n");
  6575. return -EINVAL;
  6576. }
  6577. if (params->qsync_update) {
  6578. enable = (params->qsync_mode > 0) ? true : false;
  6579. rc = dsi_display_qsync(display, enable);
  6580. if (rc)
  6581. pr_err("%s failed to send qsync commands\n",
  6582. __func__);
  6583. SDE_EVT32(params->qsync_mode, rc);
  6584. }
  6585. return rc;
  6586. }
  6587. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6588. {
  6589. if (display->panel_id != ~0x0 &&
  6590. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6591. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6592. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6593. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6594. 0, ((display->panel_id & 0xffffffff00000000) >> 31),
  6595. (display->panel_id & 0xffffffff), 0, 0);
  6596. }
  6597. }
  6598. int dsi_display_enable(struct dsi_display *display)
  6599. {
  6600. int rc = 0;
  6601. struct dsi_display_mode *mode;
  6602. if (!display || !display->panel) {
  6603. DSI_ERR("Invalid params\n");
  6604. return -EINVAL;
  6605. }
  6606. if (!display->panel->cur_mode) {
  6607. DSI_ERR("no valid mode set for the display\n");
  6608. return -EINVAL;
  6609. }
  6610. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6611. /*
  6612. * Engine states and panel states are populated during splash
  6613. * resource/trusted vm and hence we return early
  6614. */
  6615. if (is_skip_op_required(display)) {
  6616. dsi_display_config_ctrl_for_cont_splash(display);
  6617. rc = dsi_display_splash_res_cleanup(display);
  6618. if (rc) {
  6619. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6620. rc);
  6621. return -EINVAL;
  6622. }
  6623. display->panel->panel_initialized = true;
  6624. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6625. dsi_display_panel_id_notification(display);
  6626. return 0;
  6627. }
  6628. mutex_lock(&display->display_lock);
  6629. mode = display->panel->cur_mode;
  6630. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6631. rc = dsi_panel_post_switch(display->panel);
  6632. if (rc) {
  6633. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6634. display->name, rc);
  6635. goto error;
  6636. }
  6637. } else if (!(display->panel->cur_mode->dsi_mode_flags &
  6638. DSI_MODE_FLAG_POMS)){
  6639. rc = dsi_panel_enable(display->panel);
  6640. if (rc) {
  6641. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6642. display->name, rc);
  6643. goto error;
  6644. }
  6645. }
  6646. dsi_display_panel_id_notification(display);
  6647. /* Block sending pps command if modeset is due to fps difference */
  6648. if ((mode->priv_info->dsc_enabled ||
  6649. mode->priv_info->vdc_enabled) &&
  6650. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6651. rc = dsi_panel_update_pps(display->panel);
  6652. if (rc) {
  6653. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6654. display->name, rc);
  6655. goto error;
  6656. }
  6657. }
  6658. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6659. rc = dsi_panel_switch(display->panel);
  6660. if (rc)
  6661. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6662. display->name, rc);
  6663. goto error;
  6664. }
  6665. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6666. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6667. rc = dsi_display_vid_engine_enable(display);
  6668. if (rc) {
  6669. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6670. display->name, rc);
  6671. goto error_disable_panel;
  6672. }
  6673. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6674. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6675. rc = dsi_display_cmd_engine_enable(display);
  6676. if (rc) {
  6677. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6678. display->name, rc);
  6679. goto error_disable_panel;
  6680. }
  6681. } else {
  6682. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6683. rc = -EINVAL;
  6684. goto error_disable_panel;
  6685. }
  6686. goto error;
  6687. error_disable_panel:
  6688. (void)dsi_panel_disable(display->panel);
  6689. error:
  6690. mutex_unlock(&display->display_lock);
  6691. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6692. return rc;
  6693. }
  6694. int dsi_display_post_enable(struct dsi_display *display)
  6695. {
  6696. int rc = 0;
  6697. if (!display) {
  6698. DSI_ERR("Invalid params\n");
  6699. return -EINVAL;
  6700. }
  6701. mutex_lock(&display->display_lock);
  6702. if (display->panel->cur_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) {
  6703. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6704. dsi_panel_mode_switch_to_cmd(display->panel);
  6705. if (display->config.panel_mode == DSI_OP_VIDEO_MODE)
  6706. dsi_panel_mode_switch_to_vid(display->panel);
  6707. } else {
  6708. rc = dsi_panel_post_enable(display->panel);
  6709. if (rc)
  6710. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  6711. display->name, rc);
  6712. }
  6713. /* remove the clk vote for CMD mode panels */
  6714. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6715. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6716. DSI_ALL_CLKS, DSI_CLK_OFF);
  6717. mutex_unlock(&display->display_lock);
  6718. return rc;
  6719. }
  6720. int dsi_display_pre_disable(struct dsi_display *display)
  6721. {
  6722. int rc = 0;
  6723. if (!display) {
  6724. DSI_ERR("Invalid params\n");
  6725. return -EINVAL;
  6726. }
  6727. mutex_lock(&display->display_lock);
  6728. /* enable the clk vote for CMD mode panels */
  6729. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6730. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6731. DSI_ALL_CLKS, DSI_CLK_ON);
  6732. if (display->poms_pending) {
  6733. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6734. dsi_panel_pre_mode_switch_to_video(display->panel);
  6735. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6736. /*
  6737. * Add unbalanced vote for clock & cmd engine to enable
  6738. * async trigger of pre video to cmd mode switch.
  6739. */
  6740. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6741. DSI_ALL_CLKS, DSI_CLK_ON);
  6742. if (rc) {
  6743. DSI_ERR("[%s]failed to enable all clocks,rc=%d",
  6744. display->name, rc);
  6745. goto exit;
  6746. }
  6747. rc = dsi_display_cmd_engine_enable(display);
  6748. if (rc) {
  6749. DSI_ERR("[%s]failed to enable cmd engine,rc=%d",
  6750. display->name, rc);
  6751. goto error_disable_clks;
  6752. }
  6753. dsi_panel_pre_mode_switch_to_cmd(display->panel);
  6754. }
  6755. } else {
  6756. rc = dsi_panel_pre_disable(display->panel);
  6757. if (rc)
  6758. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  6759. display->name, rc);
  6760. }
  6761. goto exit;
  6762. error_disable_clks:
  6763. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6764. DSI_ALL_CLKS, DSI_CLK_OFF);
  6765. if (rc)
  6766. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  6767. display->name, rc);
  6768. exit:
  6769. mutex_unlock(&display->display_lock);
  6770. return rc;
  6771. }
  6772. static void dsi_display_handle_poms_te(struct work_struct *work)
  6773. {
  6774. struct dsi_display *display = NULL;
  6775. struct delayed_work *dw = to_delayed_work(work);
  6776. struct mipi_dsi_device *dsi = NULL;
  6777. struct dsi_panel *panel = NULL;
  6778. int rc = 0;
  6779. display = container_of(dw, struct dsi_display, poms_te_work);
  6780. if (!display || !display->panel) {
  6781. DSI_ERR("Invalid params\n");
  6782. return;
  6783. }
  6784. panel = display->panel;
  6785. mutex_lock(&panel->panel_lock);
  6786. if (!dsi_panel_initialized(panel)) {
  6787. rc = -EINVAL;
  6788. goto error;
  6789. }
  6790. dsi = &panel->mipi_device;
  6791. rc = mipi_dsi_dcs_set_tear_off(dsi);
  6792. error:
  6793. mutex_unlock(&panel->panel_lock);
  6794. if (rc < 0)
  6795. DSI_ERR("failed to set tear off\n");
  6796. }
  6797. int dsi_display_disable(struct dsi_display *display)
  6798. {
  6799. int rc = 0;
  6800. if (!display) {
  6801. DSI_ERR("Invalid params\n");
  6802. return -EINVAL;
  6803. }
  6804. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6805. mutex_lock(&display->display_lock);
  6806. /* cancel delayed work */
  6807. if (display->poms_pending &&
  6808. display->panel->poms_align_vsync)
  6809. cancel_delayed_work_sync(&display->poms_te_work);
  6810. rc = dsi_display_wake_up(display);
  6811. if (rc)
  6812. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  6813. display->name, rc);
  6814. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6815. rc = dsi_display_vid_engine_disable(display);
  6816. if (rc)
  6817. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  6818. display->name, rc);
  6819. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6820. /**
  6821. * On POMS request , disable panel TE through
  6822. * delayed work queue.
  6823. */
  6824. if (display->poms_pending &&
  6825. display->panel->poms_align_vsync) {
  6826. INIT_DELAYED_WORK(&display->poms_te_work,
  6827. dsi_display_handle_poms_te);
  6828. queue_delayed_work(system_wq,
  6829. &display->poms_te_work,
  6830. msecs_to_jiffies(100));
  6831. }
  6832. rc = dsi_display_cmd_engine_disable(display);
  6833. if (rc)
  6834. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  6835. display->name, rc);
  6836. } else {
  6837. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6838. rc = -EINVAL;
  6839. }
  6840. if (!display->poms_pending && !is_skip_op_required(display)) {
  6841. rc = dsi_panel_disable(display->panel);
  6842. if (rc)
  6843. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  6844. display->name, rc);
  6845. }
  6846. if (is_skip_op_required(display)) {
  6847. /* applicable only for trusted vm */
  6848. display->panel->panel_initialized = false;
  6849. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  6850. }
  6851. mutex_unlock(&display->display_lock);
  6852. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6853. return rc;
  6854. }
  6855. int dsi_display_update_pps(char *pps_cmd, void *disp)
  6856. {
  6857. struct dsi_display *display;
  6858. if (pps_cmd == NULL || disp == NULL) {
  6859. DSI_ERR("Invalid parameter\n");
  6860. return -EINVAL;
  6861. }
  6862. display = disp;
  6863. mutex_lock(&display->display_lock);
  6864. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  6865. mutex_unlock(&display->display_lock);
  6866. return 0;
  6867. }
  6868. int dsi_display_dump_clks_state(struct dsi_display *display)
  6869. {
  6870. int rc = 0;
  6871. if (!display) {
  6872. DSI_ERR("invalid display argument\n");
  6873. return -EINVAL;
  6874. }
  6875. if (!display->clk_mngr) {
  6876. DSI_ERR("invalid clk manager\n");
  6877. return -EINVAL;
  6878. }
  6879. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  6880. DSI_ERR("invalid clk handles\n");
  6881. return -EINVAL;
  6882. }
  6883. mutex_lock(&display->display_lock);
  6884. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  6885. if (rc) {
  6886. DSI_ERR("failed to dump dsi clock state\n");
  6887. goto end;
  6888. }
  6889. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  6890. if (rc) {
  6891. DSI_ERR("failed to dump mdp clock state\n");
  6892. goto end;
  6893. }
  6894. end:
  6895. mutex_unlock(&display->display_lock);
  6896. return rc;
  6897. }
  6898. int dsi_display_unprepare(struct dsi_display *display)
  6899. {
  6900. int rc = 0, i;
  6901. struct dsi_display_ctrl *ctrl;
  6902. if (!display) {
  6903. DSI_ERR("Invalid params\n");
  6904. return -EINVAL;
  6905. }
  6906. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6907. mutex_lock(&display->display_lock);
  6908. rc = dsi_display_wake_up(display);
  6909. if (rc)
  6910. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  6911. display->name, rc);
  6912. if (!display->poms_pending && !is_skip_op_required(display)) {
  6913. rc = dsi_panel_unprepare(display->panel);
  6914. if (rc)
  6915. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  6916. display->name, rc);
  6917. }
  6918. /* Remove additional vote added for pre_mode_switch_to_cmd */
  6919. if (display->poms_pending &&
  6920. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6921. display_for_each_ctrl(i, display) {
  6922. ctrl = &display->ctrl[i];
  6923. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  6924. continue;
  6925. flush_workqueue(display->dma_cmd_workq);
  6926. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  6927. ctrl->ctrl->dma_wait_queued = false;
  6928. }
  6929. dsi_display_cmd_engine_disable(display);
  6930. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6931. DSI_ALL_CLKS, DSI_CLK_OFF);
  6932. }
  6933. rc = dsi_display_ctrl_host_disable(display);
  6934. if (rc)
  6935. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  6936. display->name, rc);
  6937. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6938. DSI_LINK_CLK, DSI_CLK_OFF);
  6939. if (rc)
  6940. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  6941. display->name, rc);
  6942. rc = dsi_display_ctrl_deinit(display);
  6943. if (rc)
  6944. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  6945. display->name, rc);
  6946. if (!display->panel->ulps_suspend_enabled) {
  6947. rc = dsi_display_phy_disable(display);
  6948. if (rc)
  6949. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  6950. display->name, rc);
  6951. }
  6952. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6953. DSI_CORE_CLK, DSI_CLK_OFF);
  6954. if (rc)
  6955. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  6956. display->name, rc);
  6957. /* destrory dsi isr set up */
  6958. dsi_display_ctrl_isr_configure(display, false);
  6959. if (!display->poms_pending && !is_skip_op_required(display)) {
  6960. rc = dsi_panel_post_unprepare(display->panel);
  6961. if (rc)
  6962. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  6963. display->name, rc);
  6964. }
  6965. mutex_unlock(&display->display_lock);
  6966. /* Free up DSI ERROR event callback */
  6967. dsi_display_unregister_error_handler(display);
  6968. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6969. return rc;
  6970. }
  6971. void __init dsi_display_register(void)
  6972. {
  6973. dsi_phy_drv_register();
  6974. dsi_ctrl_drv_register();
  6975. dsi_display_parse_boot_display_selection();
  6976. platform_driver_register(&dsi_display_driver);
  6977. }
  6978. void __exit dsi_display_unregister(void)
  6979. {
  6980. platform_driver_unregister(&dsi_display_driver);
  6981. dsi_ctrl_drv_unregister();
  6982. dsi_phy_drv_unregister();
  6983. }
  6984. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  6985. 0600);
  6986. MODULE_PARM_DESC(dsi_display0,
  6987. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  6988. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  6989. 0600);
  6990. MODULE_PARM_DESC(dsi_display1,
  6991. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");